HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 77

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table C-7: Display Instructions (Continued)
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
This instruction sets the address of the display data page. Any RAM data bit can be accessed when its page address and column address are
specified. Changing the Page Address does not affect the display status.
This instruction sets the address of the display data RAM. When a read or write to or from the display data RAM occurs, the addresses are
automatically increased.
This instruction changes the relationship between RAM column address and segment driver.
ADC = 0, SEG1 --> SEG132
ADC = 1, SEG132 --> SEG1
Set column address MSB
Set column address LSB
Set page address
Instruction
ADC select
R
default mode
RS
Y7
0
0
0
0
..
1
1
0
0
RW
Y6
0
0
0
0
0
..
1
1
0
DB7
Y5
1
0
0
0
0
..
1
1
1
www.xilinx.com
DB6
P3
Y4
0
0
0
..
0
1
0
0
0
0
..
1
1
0
DB5
P2
Y3
1
0
0
..
1
0
0
0
0
0
..
1
1
1
DB4
Y2
P1
1
0
0
..
1
0
1
0
0
0
..
1
1
0
DB3
P3
P0
Y7
Y3
Y1
0
1
..
1
0
0
0
..
1
1
0
Hardware Schematic Diagram
page 0
page 1
page 7
page 8
DB2
P2
Y6
Y2
Y0
0
1
..
0
1
0
Addr 0
Addr 1
Addr
Addr
DB1
Col
Col
Col
130
Col
131
Y5
Y1
P1
...
0
ADC
DB0
Y4
Y0
P0
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