HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 7

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

About This Guide
Guide Contents
Additional Documentation
ML550 Networking Interfaces Platform
UG202 (v1.4) April 18, 2008
R
This user guide is a description of the Virtex
Development Board. Complete and up-to-date documentation of the Virtex-5 family of
FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5.
This manual contains the following chapters:
The following documents are also available for download at
http://www.xilinx.com/virtex5.
Chapter 1, “Introduction”
Chapter 2, “Getting Started”
Chapter 3, “Hardware Description”
Chapter 4, “Configuration”
Appendix A, “LVDS”
Appendix B, “LVDS Loopback Board”
Appendix C, “LCD Interface”
Appendix D, “ML550 Starter UCF”
Virtex-5 Family Overview
The features and product selection of the Virtex-5 family are outlined in this overview.
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-5 family.
Virtex-5 FPGA User Guide
Chapters in this guide cover the following topics:
-
-
-
-
-
-
Clocking Resources
Clock Management Technology (CMT)
Phase-Locked Loops (PLLs)
Block RAM
Configurable Logic Blocks (CLBs)
SelectIO™ Resources
www.xilinx.com
®
-5 FPGA ML550 Networking Interfaces
Preface
7