MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 90

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

88
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is cleared to 0 and the
(b) After RESET release, the CPU clock can be switched from the internal low-speed oscillation clock to the
(c) Internal low-speed oscillator can be set to stopped/oscillating using the internal oscillation mode register
(d) When the internal low-speed oscillation clock is used as the CPU clock, the high-speed system clock can be
(e) The oscillation stabilization time (2
internal low-speed oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17
clocks of the internal low-speed oscillation clock have elapsed after RESET release (or clock supply to the
CPU stops for 17 clocks). During the RESET period, oscillation of the high-speed system clock and internal
low-speed oscillation clock is stopped.
high-speed system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed
system clock oscillation stabilization time has elapsed. At this time, in the case of an X1 clock, check the
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) before
switching the CPU
software before switching the CPU
(RCM) when “Can be stopped by software” is selected for the internal low-speed oscillator by an option byte,
if the high-speed system clock is used as the CPU clock. Make sure that MCS is 1 at this time.
set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.
time select register (OSTS) is secured when releasing STOP mode while the high-speed system clock is
being used as the CPU clock.
In addition, when RESET is released, and when the STOP mode is released while the internal low-speed
oscillation clock is being used as the CPU clock, there is no oscillation stabilization time wait.
When switching to the high-speed system clock as the CPU clock, in the case of an X1 clock, check the
oscillation stabilization time by using the oscillation stabilization time counter status register (OSTC). In the
case of an internal high-speed oscillation clock, secure wait time (350 s) by software.
clock.
In the case of an internal high-speed oscillation
CHAPTER 5 CLOCK GENERATOR
11
clock.
/f
User’s Manual U17890EJ2V0UD
XP
, 2
The CPU clock status can be checked using bit 1 (MCS) of MCM.
13
/f
XP
, 2
14
/f
XP
, 2
15
/f
XP
, 2
16
/f
XP
) selected by the oscillation stabilization
clock,
secure wait time (350 s) by