MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 180

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(3) When the CPU clock is the internal low-speed oscillation clock (f
178
Note Confirm the oscillation stabilization time of f
CPU operation
CPU operation
clock is the X1 input clock (f
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds
its value.
<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.
<2> The CPU clock is switched to the X1 input clock (f
<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time
<2> Timing when counting is started after the CPU clock is switched to the X1 input clock (f
Watchdog timer
Watchdog timer
(OSTC).
select register (OSTS) has elapsed
(CPU Clock: Internal Low-speed Oscillation Clock, WDT Operation Clock: X1 Input Clock)
(Internal low-speed
f
f
XP
f
f
RL
Normal operation
(internal low-speed
XP
RL
oscillation clock)
Normal operation
oscillation clock)
Operating
Operating
XP
Oscillation
) when the STOP instruction is executed
Oscillation
stopped
stopped
STOP
STOP
Figure 9-6. Operation in STOP Mode
CHAPTER 9 WATCHDOG TIMER
User’s Manual U17890EJ2V0UD
Operation stopped
Operation stopped
Clock supply stopped Normal operation (Internal low-speed oscillation clock)
(internal low-speed
Oscillation stabilization time
Oscillation stabilization time
Normal operation
oscillation clock)
(set by OSTS register)
Clock supply
XP
(set by OSTS register)
17 clocks
17 clocks
stopped
using the oscillation stabilization time counter status register
XP
).
CPU clock
f
RL
RL
Normal operation (X1 input clock)
) and the watchdog timer operation
f
XP
Note
Operating
Operating
XP
)