MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 302

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3 Registers Controlling Low-Voltage Detector
(1) Low-voltage detection register (LVIM)
300
The low-voltage detector is controlled by the following register.
Address: FF78H
Symbol
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
LVIM
Low-voltage detection register (LVIM)
Notes 1.
Caution To stop LVI, follow either of the procedures below.
LVION
LVIMD
LVIF
LVION
7
0
1
0
1
0
1
Notes 2, 3
Note 4
2.
3.
4.
Note 2
After reset: 00H
Bit 0 is read-only.
LVION and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are
not cleared to 0 in the case of an LVI reset.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVIMD to 0 first, and then
Disables operation
Enables operation
Generates interrupt signal when supply voltage (V
Generates internal reset signal when supply voltage (V
Supply voltage (V
Supply voltage (V
Figure 20-2. Format of Low-Voltage Detection Register (LVIM)
6
0
CHAPTER 20 LOW-VOLTAGE DETECTOR
R/W
DD
DD
5
0
Note 1
) > detection voltage (V
) < detection voltage (V
Low-voltage detection operation mode selection
User’s Manual U17890EJ2V0UD
Enables low-voltage detection operation
4
0
Low-voltage detection flag
LVI
LVI
3
0
), or when operation is disabled
)
DD
) < detection voltage (V
DD
) < detection voltage (V
2
0
clear LVION to 0.
LVIMD
1
LVI
)
LVI
LVIF
)
0