MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 179
MC-78F0712-KIT
Manufacturer Part Number
MC-78F0712-KIT
Description
KIT REF SYSTEM 78K0 UPD78F0712
Manufacturer
Renesas Electronics America
Specifications of MC-78F0712-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.4.3
internal low-speed oscillation clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (f
(2) When the CPU clock is the X1 input clock (f
The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
speed oscillation clock (f
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Watchdog timer
Watchdog timer
CPU operation
CPU operation
Watchdog timer operation in STOP mode (when “Internal low-speed oscillation can be stopped by
software” is selected by option byte)
Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
(CPU Clock: X1 Input Clock, WDT Operation Clock: Internal Low-speed Oscillation Clock)
f
f
f
f
XP
RL
XP
RL
operation
Operating
operation
Operating Operation stopped
Normal
Normal
RL
) when the STOP instruction is executed
Oscillation
Oscillation
stopped
stopped
STOP
STOP
Figure 9-5. Operation in STOP Mode
CHAPTER 9 WATCHDOG TIMER
User’s Manual U17890EJ2V0UD
Operation stopped
Oscillation stabilization time
Oscillation stabilization time
Oscillation stabilization time
Oscillation stabilization time
XP
) and the watchdog timer operation clock is the internal low-
(set by OSTS register)
(set by OSTS register)
Operating
Normal operation
Normal operation
Operating
XP
) when the STOP
177
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