MC-78F0712-KIT Renesas Electronics America, MC-78F0712-KIT Datasheet - Page 281

• Manufacturer Part Number: MC-78F0712-KIT
• Description: KIT REF SYSTEM 78K0 UPD78F0712
• Manufacturer: Renesas Electronics America

Specifications of MC-78F0712-KIT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2 Standby Function Operation
17.2.1 HALT mode
(1) HALT mode
Notes 1.
Item
System clock
CPU
Port (latch)
10-bit inverter control timer
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer/event counter 51
Watchdog
timer
Hi-Z output controller
Real-time output ports
A/D converter
Serial
interface
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock or internal low-speed oscillation clock.
The operating statuses in the HALT mode are shown below.
2.
HALT Mode Setting
Internal
speed
cannot be
stopped
Internal
speed
can be stopped
UART00
When “Stopped by software” is selected for internal low-speed oscillator by an option byte and internal low-
speed oscillator is stopped by software (for option bytes, see CHAPTER 21 OPTION BYTES).
“Internal low-speed oscillator cannot be stopped” or “Internal low-speed oscillator can be stopped by
software” can be selected by an option byte.
oscillator
oscillator
Note 2
low-
low-
Note 2
Clock supply to the CPU is stopped.
Operation stopped
Status before HALT mode was set is retained
Operable
Operable
Operable
Operable
Operable
Operation stopped
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
When Internal Low-speed
When HALT Instruction Is Executed While CPU Is
Oscillation Clock
Table 17-2. Operating Statuses in HALT Mode
Operating on High-speed System Clock
Continues
CHAPTER 17 STANDBY FUNCTION
User’s Manual U17890EJ2V0UD
When Internal Low-speed
Oscillation Clock
Stopped
Note 1
Operation not guaranteed
Operation not guaranteed
Operation not guaranteed when count clock other than
TI50 is selected
Operation not guaranteed when count clock other than
f
Operable
Operation not guaranteed
Operation not guaranteed
Operation not guaranteed when serial clock other than
TM50 output is selected during 8-bit timer/event counter
50 operation
Operation not guaranteed
When High-speed System
RL
/2
When HALT Instruction Is Executed While CPU Is
Operating on Internal Low-speed Oscillation Clock
7
Clock Oscillation
is selected
Continues
When High-speed System
Clock Oscillation Stopped
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