C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 69

• Manufacturer Part Number: C8051F996DK
• Description: KIT DEV FOR C8051F996
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F996DK

• Contents: Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
• Processor To Be Evaluated: C8051F996
• Processor Series: C8051F98x
• Interface Type: USB
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F996
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1963

5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or
V
requirements as well as the mux impedance and sampling capacitor values.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
DD
TOTAL
with respect to GND, R
is the sum of the AMUX0 resistance and any external source resistance.
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.10 for details.
Equation 5.1. ADC0 Settling Time Requirements
Figure 5.4. ADC0 Equivalent Input Circuits
P0.x
TOTAL
t
=
reduces to R
RC
ln
MUX Select
Input


------ -
SA
2
= R
n


MUX

Rev. 1.0
R
* C
MUX
TOTAL
R
MUX
SAMPLE
. See Table 4.10 for ADC0 minimum settling time
C8051F99x-C8051F98x
C
SAMPLE
C
SAMPLE
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