C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 218

• Manufacturer Part Number: C8051F996DK
• Description: KIT DEV FOR C8051F996
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F996DK

• Contents: Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
• Processor To Be Evaluated: C8051F996
• Processor Series: C8051F98x
• Interface Type: USB
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F996
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1963

C8051F99x-C8051F98x
218
Figure 21.4. Crossbar Priority Decoder in Example Configuration (No Pins Skipped)
Figure 21.5. Crossbar Priority Decoder in Example Configuration (4 Pins Skipped)
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
Port pin assigned to peripheral by the Crossbar
Special Function Signals are not assigned by the Crossbar. When
these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
0
0
Port pin assigned to peripheral by the Crossbar
Special Function Signals are not assigned by the Crossbar. When
these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
0
0
1
0
1
0
2
1
2
0
P0SKIP[0:7]
P0SKIP[0:7]
3
1
3
0
P0
P0
4
0
4
0
5
0
5
0
6
0
6
0
7
0
7
0
0
1
0
0
1
1
1
0
Rev. 1.0
2
0
2
0
P1SKIP[0:7]
P1SKIP[0:7]
3
0
3
0
P1
P1
4
0
4
0
*NSS is only pinned out in 4-wire SPI mode
Note: In this example, CP0, CP0A, and SYSCLK
are not selected in the Crossbar.
*NSS is only pinned out in 4-wire SPI mode
Note: In this example, CP0, CP0A, and SYSCLK
are not selected in the Crossbar.
5
0
5
0
6
0
6
0
7
0
7
0
0
0
0
0
C8051F98x-C8051F99x devices
C8051F98x-C8051F99x devices
P2.0 - P2.6 not available on
P2.0 - P2.6 not available on
1
0
1
0
2
0
2
0
P2SKIP[0:7]
P2SKIP[0:7]
3
0
P2
3
0
P2
4
0
4
0
5
0
5
0
6
0
6
0
7
0
7
0