C8051F996DK Silicon Laboratories Inc, C8051F996DK Datasheet - Page 256
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C8051F996DK
Manufacturer Part Number
C8051F996DK
Description
KIT DEV FOR C8051F996
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets
1.C8051F996DK.pdf
(24 pages)
2.C8051F996DK.pdf
(2 pages)
3.C8051F996DK.pdf
(4 pages)
4.C8051F996DK.pdf
(322 pages)
Specifications of C8051F996DK
Contents
Board, Batteries, Cables, CDs, Debug Adapter, Documentation, Power Adapter
Processor To Be Evaluated
C8051F996
Processor Series
C8051F98x
Interface Type
USB
Operating Supply Voltage
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F996
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1963
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C8051F99x-C8051F98x
23.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “25.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 280). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 23.1-A
and Equation 23.1-B.
Where T1
value). Timer 1 clock frequency is selected as described in Section “25.1. Timer 0 and Timer 1” on
page 278. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1
through Table 23.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
256
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
A)
B)
UartBaudRate
T1_Overflow_Rate
Figure 23.2. UART0 Baud Rate Logic
RX Timer
Equation 23.1. UART0 Baud Rate
Timer 1
TH1
TL1
=
Overflow
Overflow
Rev. 1.0
1
-- -
2
=
T1_Overflow_Rate
------------------------- -
256 TH1
T1
–
CLK
2
2
UART
RX Clock
TX Clock
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