DV164136 Microchip Technology, DV164136 Datasheet - Page 438

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 352
H
Hardware Multiplier .......................................................... 111
I
I/O Ports ........................................................................... 129
I
INCF ................................................................................. 352
INCFSZ ............................................................................ 353
In-Circuit Debugger .......................................................... 329
DS39778D-page 438
2
C Mode (MSSP)
Table Pointer Boundaries .......................................... 92
Table Reads and Table Writes .................................. 89
Write Sequence ......................................................... 95
Write Sequence (Word Programming) ....................... 97
Writing ........................................................................ 95
8 x 8 Multiplication Algorithms ................................. 111
Operation ................................................................. 111
Performance Comparison (table) ............................. 111
Input Pull-up Configuration ...................................... 130
Open-Drain Outputs ................................................. 130
Pin Capabilities ........................................................ 129
Acknowledge Sequence Timing ............................... 262
Associated Registers ............................................... 270
Baud Rate Generator ............................................... 255
Bus Collision
Clock Arbitration ....................................................... 256
Clock Stretching ....................................................... 248
Clock Synchronization and the CKP bit ................... 249
Effects of a Reset ..................................................... 263
General Call Address Support ................................. 252
I
Master Mode ............................................................ 253
Multi-Master Communication, Bus Collision and Arbitra-
Multi-Master Mode ................................................... 263
Operation ................................................................. 238
Read/Write Bit Information (R/W Bit) ............... 238, 241
Registers .................................................................. 233
Serial Clock (RC3/SCKx/SCLx) ............................... 241
Slave Mode .............................................................. 238
Sleep Operation ....................................................... 263
Stop Condition Timing .............................................. 262
2
C Clock Rate w/BRG ............................................. 255
Boundaries Based on Operation ........................ 92
Unexpected Termination .................................... 98
Write Verify ........................................................ 98
During a Repeated Start Condition .................. 267
During a Stop Condition ................................... 269
10-Bit Slave Receive Mode (SEN = 1) ............. 248
10-Bit Slave Transmit Mode ............................. 248
7-Bit Slave Receive Mode (SEN = 1) ............... 248
7-Bit Slave Transmit Mode ............................... 248
Operation ......................................................... 254
Reception ......................................................... 259
Repeated Start Condition Timing ..................... 258
Start Condition Timing ..................................... 257
Transmission .................................................... 259
tion ................................................................... 263
Address Masking Modes
Addressing ....................................................... 238
Reception ......................................................... 241
Transmission .................................................... 241
5-Bit ......................................................... 239
7-Bit ......................................................... 240
In-Circuit Serial Programming (ICSP) ...................... 315, 329
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 378
Indirect Addressing ............................................................ 84
INFSNZ ............................................................................ 353
Initialization Conditions for all Registers ...................... 57–62
Instruction Cycle ................................................................ 70
Instruction Set .................................................................. 331
and Standard PIC18 Instructions ............................. 378
Clocking Scheme ....................................................... 70
Flow/Pipelining ........................................................... 70
ADDLW .................................................................... 337
ADDWF .................................................................... 337
ADDWF (Indexed Literal Offset Mode) .................... 379
ADDWFC ................................................................. 338
ANDLW .................................................................... 338
ANDWF .................................................................... 339
BC ............................................................................ 339
BCF ......................................................................... 340
BN ............................................................................ 340
BNC ......................................................................... 341
BNN ......................................................................... 341
BNOV ...................................................................... 342
BNZ ......................................................................... 342
BOV ......................................................................... 345
BRA ......................................................................... 343
BSF .......................................................................... 343
BSF (Indexed Literal Offset Mode) .......................... 379
BTFSC ..................................................................... 344
BTFSS ..................................................................... 344
BTG ......................................................................... 345
BZ ............................................................................ 346
CALL ........................................................................ 346
CLRF ....................................................................... 347
CLRWDT ................................................................. 347
COMF ...................................................................... 348
CPFSEQ .................................................................. 348
CPFSGT .................................................................. 349
CPFSLT ................................................................... 349
DAW ........................................................................ 350
DCFSNZ .................................................................. 351
DECF ....................................................................... 350
DECFSZ .................................................................. 351
Extended Instructions .............................................. 373
General Format ........................................................ 333
GOTO ...................................................................... 352
INCF ........................................................................ 352
INCFSZ .................................................................... 353
INFSNZ .................................................................... 353
IORLW ..................................................................... 354
IORWF ..................................................................... 354
LFSR ....................................................................... 355
MOVF ...................................................................... 355
MOVFF .................................................................... 356
MOVLB .................................................................... 356
MOVLW ................................................................... 357
MOVWF ................................................................... 357
MULLW .................................................................... 358
MULWF .................................................................... 358
NEGF ....................................................................... 359
NOP ......................................................................... 359
Opcode Field Descriptions ....................................... 332
Considerations when Enabling ........................ 378
Syntax .............................................................. 373
Use with MPLAB IDE Tools ............................. 380
© 2009 Microchip Technology Inc.