DV164136 Microchip Technology, DV164136 Datasheet - Page 150

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
TABLE 10-18: PORTH FUNCTIONS (CONTINUED)
TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
DS39778D-page 150
RH7/PMWR/
AN15/P1B
Legend:
Note 1:
PORTH
LATH
TRISH
ANCON1
Legend: Shaded cells are not used by PORTH.
Note 1:
Pin Name
Name
(1)
2:
2:
(1)
(1)
(2)
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
Unimplemented on 64-pin devices, read as ‘0’.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
PCFG15
TRISH7
LATH7
Function
PMWR
Bit 7
RH7
P1B
AN15
RH7
(1)
(2)
PCFG14
Setting
TRISH6
LATH6
TRIS
Bit 6
RH6
0
1
x
x
0
I/O
O
O
O
I
I
I
PCFG13
TRISH5
LATH5
Bit 5
RH5
Type
ANA
DIG
DIG
TTL
DIG
I/O
ST
PCFG12
LATH<7> data output.
PORTH<7> data input.
Parallel Master Port write strobe.
Parallel Master Port write in.
A/D input channel 15. Default input configuration on POR; does not affect
digital output.
ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
TRISH4
LATH4
Bit 4
RH4
PCFG11
TRISH3
LATH3
Bit 3
RH3
PCFG10
TRISH2
LATH2
Bit 2
RH2
Description
TRISH1
PCFG9
LATH1
Bit 1
RH1
© 2009 Microchip Technology Inc.
TRISH0
PCFG8
LATH0
Bit 0
RH0
on Page:
Values
Reset
60
61
60
59