DV164136 Microchip Technology, DV164136 Datasheet - Page 404

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
FIGURE 27-5:
TABLE 27-9:
DS39778D-page 404
10
11
12
13
14
15
16
17
18
19
20
21
22†
23†
Note 1:
Param
No.
Note:
(Output)
I/O pin
I/O pin
(Input)
OSC1
CLKO
† These parameters are asynchronous events not related to any internal clock edges.
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OS
OS
CK
CK
CK
CK
OS
OS
Symbol
IO
IO
IO
IO
INP
RBP
Measurements are taken in EC mode, where CLKO output is 4 x T
V2
V2
R
F
H2
R
F
L2
H2
H2
H2
H2
Refer to Figure 27-3 for load conditions.
CK
OS
IO
CK
IO
CK
IO
IO
V CLKO ↓ to Port Out Valid
H Port In Valid before CLKO ↑
I
V OSC1 ↑ (Q1 cycle) to Port Out Valid
I
H Port Input Valid to OSC1 ↑
H OSC1 ↑ to CLKO ↑
L OSC1 ↑ to CLKO ↓
CLKO AND I/O TIMING REQUIREMENTS
CLKO Rise Time
CLKO Fall Time
Port In Hold after CLKO ↑
OSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
(I/O in setup time)
Port Output Rise Time
Port Output Fall Time
INTx pin High or Low Time
RB7:RB4 Change INTx High or Low Time
CLKO AND I/O TIMING
Old Value
Q4
Characteristic
10
13
17
14
20, 21
Q1
19
0.25 T
18
Min
100
T
T
—
—
—
—
—
—
—
—
CY
CY
CY
0
0
+ 25
Q2
15
New Value
OSC
Typ
75
75
15
15
50
—
—
—
—
—
—
—
—
—
.
0.5 T
© 2009 Microchip Technology Inc.
Max
200
200
150
30
30
CY
—
—
—
—
—
—
6
5
11
12
+ 20
16
Units Conditions
Q3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)