DV164136 Microchip Technology, DV164136 Datasheet - Page 189

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
The Timer2 module incorporates the following features:
• 8-Bit Timer and Period registers (TMR2 and PR2,
• Readable and writable (both registers)
• Software programmable prescaler
• Software programmable postscaler
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
The module is controlled through the T2CON register
(Register 14-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 14-1.
REGISTER 14-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1-0
respectively)
(1:1, 1:4 and 1:16)
(1:1 through 1:16)
MSSP modules
U-0
—
TIMER2 MODULE
Unimplemented: Read as ‘0’
T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
T2OUTPS3
R/W-0
T2CON: TIMER2 CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
T2OUTPS2
R/W-0
T2OUTPS1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
T2OUTPS0
PIC18F87J11 FAMILY
R/W-0
14.1
In normal operation, TMR2 is incremented from 00h on
each clock (F
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the
(T2CON<1:0>). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the
“Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
TMR2 is not cleared when T2CON is written.
Watchdog Timer Reset or Brown-out Reset)
output
prescaler
Timer2 Operation
TMR2ON
OSC
counter/postscaler
R/W-0
/4). A 4-bit counter/prescaler on the
control
x = Bit is unknown
bits,
T2CKPS1
R/W-0
T2CKPS1:T2CKPS0
(see
DS39778D-page 189
Section 14.2
T2CKPS0
R/W-0
bit 0