DV164136 Microchip Technology, DV164136 Datasheet - Page 300
![DEVELOPMENT KIT FOR PIC18](/photos/9/21/92129/dv164136_sml.jpg)
DV164136
Manufacturer Part Number
DV164136
Description
DEVELOPMENT KIT FOR PIC18
Manufacturer
Microchip Technology
Series
PIC®r
Type
MCUr
Datasheets
1.DM183032.pdf
(38 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(6 pages)
4.DV164136.pdf
(446 pages)
5.DV164136.pdf
(4 pages)
6.DV164136.pdf
(18 pages)
Specifications of DV164136
Contents
Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
Processor To Be Evaluated
PIC18F8722, PIC18F87J11
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V, 5 V
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18F8xxx
Kit Contents
PIC18 Exp Brd PICkit 3 Cable CD PSU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PIC18F8722, PIC18F87J11
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DV164136
Manufacturer:
MICROCHIP
Quantity:
12 000
- DM183032 PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- DV164136 PDF datasheet #4
- DV164136 PDF datasheet #5
- DV164136 PDF datasheet #6
- Current page: 300 of 448
- Download datasheet (8Mb)
PIC18F87J11 FAMILY
21.5
Figure 21-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-4 shows the operation of the A/D Converter
after
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 21-3:
FIGURE 21-4:
DS39778D-page 300
Note:
(Holding capacitor continues
acquiring input)
AD
AD
Set GO/DONE bit
wait is required before the next acquisition can be
1
acquisition time before the conversion starts.
the
conversion
A/D Conversions
T
T
Set GO/DONE bit
CY
Automatic
Acquisition
Time
ACQT
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Holding capacitor is disconnected from analog input (typically 100 ns)
2
GO/DONE
- T
AD
Cycles
Conversion starts
T
3
AD
sample.
A/D CONVERSION T
A/D CONVERSION T
1 T
bit
4
AD
b9
2 T
Conversion starts
(Holding capacitor is disconnected)
has
1
This
AD
b8
3 T
been
b9
2
AD
means
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
b7
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
4 T
set,
b8
3
AD
AD
AD
b6
5 T
CYCLES (ACQT2:ACQT0 = 000, T
CYCLES (ACQT2:ACQT0 = 010, T
ADIF bit is set, holding capacitor is reconnected to analog input.
the
the
ADIF bit is set, holding capacitor is connected to analog input.
b7
4
AD
b5
6 T
T
5
b6
AD
AD
b4
7 T
Cycles
21.6
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
ACQ
b5
6
AD
b3
time is selected before the Special Event Trigger
8
Use of the ECCP2 Trigger
b4
T
7
AD
b2
9 T
b3
8
AD
b1
10
bits
T
b2
9
AD
© 2009 Microchip Technology Inc.
b0
11
ACQ
ACQ
10
(CCP2CON<3:0>)
b1
= 0)
= 4 T
b0
11
AD
)
be
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