DV164136 Microchip Technology, DV164136 Datasheet - Page 168

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
11.3.5
Up to two chip select lines, PMCS1 and PMCS2, are
available for the Master modes of the PMP. The two
chip select lines are multiplexed with the Most Signifi-
cant bits of the address bus (PMADDRH<6> and
PMADDRH<7>). When a pin is configured as a chip
select,
auto-increment/decrement. The function of the chip
select signals is configured using the chip select
function bits (PMCONL <7:6>).
11.3.6
While the module is operating in one of the Master
modes, the INCM bits (PMMODEH<3:4>) control the
behavior of the address value. The address can be
made to automatically increment or decrement after
each read and write operation. The address increments
once each operation is completed and the BUSY bit
goes to ‘0’. If the chip select signals are disabled and
configured as address bits, the bits will participate in
the increment and decrement operations; otherwise,
the CS2 and CS1 bit values will be unaffected.
11.3.7
In Master mode, the user has control over the duration
of the read, write and address cycles by configuring the
module wait states. Three portions of the cycle, the
beginning, middle, and end, are configured using the
corresponding WAITBx, WAITMx and WAITEx bits in
the PMMODEL register.
The WAITB1:WAITB0 bits (PMMODEL<7:6>) set the
number of wait cycles for the data setup prior to the
PMRD/PMWT strobe in Mode 10, or prior to the
PMENB strobe in Mode 11. The WAITM3:WAITM0 bits
(PMMODEL<5:2>) set the number of wait cycles for the
PMRD/PMWT strobe in Mode 10, or for the PMENB
strobe in Mode 11. When this wait state setting is 0,
then WAITB and WAITE have no effect. The
WAITE1:WAITE0 bits (PMMODEL<1:0>) define the
number of wait cycles for the data hold time after the
PMRD/PMWT strobe in Mode 10, or after the PMENB
strobe in Mode 11.
11.3.8
To perform a read on the Parallel Master Port, the user
reads the PMDIN1L register. This causes the PMP to
output the desired values on the chip select lines and
the address bus. Then the read line (PMRD) is strobed.
The read data is placed into the PMDIN1L register.
DS39778D-page 168
it
CHIP SELECT FEATURES
AUTO-INCREMENT/DECREMENT
WAIT STATES
READ OPERATION
is
not
included
in
any
address
If the 16-bit mode is enabled (MODE16 = 1), the read
of the low byte of the PMDIN1L register will initiate two
bus reads. The first read data byte is placed into the
PMDIN1L register, and the second read data is placed
into the PMDIN1H.
Note that the read data obtained from the PMDIN1L
register is actually the read value from the previous
read operation. Hence, the first user read will be a
dummy read to initiate the first bus read and fill the read
register. Also, the requested read value will not be
ready until after the BUSY bit is observed low. Thus, in
a back-to-back read operation, the data read from the
register will be the same for both reads. The next read
of the register will yield the new value.
11.3.9
To perform a write onto the parallel bus, the user writes
to the PMDIN1L register. This causes the module to
first output the desired values on the chip select lines
and the address bus. The write data from the PMDIN1L
register is placed onto the PMD<7:0> data bus. Then
the write line (PMWR) is strobed. If the 16-bit mode is
enabled (MODE16 = 1), the write to the PMDIN1L reg-
ister will initiate two bus writes. First write will consist of
the data contained in PMDIN1L and the second write
will contain the PMDIN1H.
11.3.10
11.3.10.1
In addition to the PMP interrupt, a BUSY bit is provided
to indicate the status of the module. This bit is only
used in Master mode. While any read or write operation
is in progress, the BUSY bit is set for all but the very last
CPU cycle of the operation. In effect, if a single-cycle
read or write operation is requested, the BUSY bit will
never be active. This allows back-to-back transfers.
While the bit is set, any request by the user to initiate a
new operation will be ignored (i.e., writing or reading
the lower byte of the PMDIN1L register will not initiate
either a read nor a write).
11.3.10.2
When the PMP module interrupt is enabled for Master
mode, the module will interrupt on every completed
read or write cycle; otherwise, the BUSY bit is available
to query the status of the module.
WRITE OPERATION
PARALLEL MASTER PORT STATUS
The BUSY Bit
INTERRUPTS
© 2009 Microchip Technology Inc.