PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 57

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 4-2:
FIGURE 4-4:
4.2.3
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-0
PUSH AND POP INSTRUCTIONS
Legend:
C = Clearable bit
- n = Value at POR
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
Unimplemented: Read as ‘0’
SP4:SP0: Stack Pointer Location bits
bit 7
STKFUL
TOSU
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
STKPTR REGISTER
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00h
R/C-0
(1)
STKUNF
TOSH
R/C-0
1Ah
R = Readable bit
‘1’ = Bit is set
(1)
PIC18F6585/8585/6680/8680
Top-of-Stack
TOSL
U-0
34h
—
Return Address Stack
R/W-0
U = Unimplemented bit, read as ‘0’ W = Writable bit
‘0’ = Bit is cleared
SP4
001A34h
000D58h
4.2.4
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the
appropriate STKFUL or STKUNF bit, but not cause a
device Reset. When the STVREN bit is enabled, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
R/W-0
SP3
STACK FULL/UNDERFLOW RESETS
11111
11110
11101
00011
00010
00001
00000
STKPTR<4:0>
R/W-0
SP2
00010
R/W-0
SP1
x = Bit is unknown
DS30491C-page 55
R/W-0
SP0
bit 0