PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 109

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.0
8.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F6585/8585/6680/8680 devices. By making
the multiply a hardware operation, it completes in a sin-
gle instruction cycle. This is an unsigned multiply that
gives a 16-bit result. The result is stored in the 16-bit
product register pair (PRODH:PRODL). The multiplier
does not affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1:
 2004 Microchip Technology Inc.
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
algorithms
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
PIC18F6585/8585/6680/8680
Program
Memory
(Words)
13
33
21
24
52
36
1
6
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
EXAMPLE 8-2:
MOVF
MULWF
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
Cycles
(Max)
242
254
69
91
24
36
1
6
Operation
ARG1, W
ARG2
ARG1, W
ARG2
ARG2, SB
PRODH
ARG2, W
ARG1, SB
PRODH
@ 40 MHz
24.2 s
25.4 s
100 ns
600 ns
6.9 s
9.1 s
2.4 s
3.6 s
8 x 8 UNSIGNED
MULTIPLY ROUTINE
8 x 8 SIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 s
14.4 s
27.6 s
36.4 s
96.8 s
Time
400 ns
2.4 s
9.6 s
DS30491C-page 107
- ARG1
- ARG2
@ 4 MHz
242 s
254 s
69 s
91 s
24 s
36 s
1 s
6 s