PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 285

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 23-3:
 2004 Microchip Technology Inc.
bit 7-6
bit 5
bit 4-0
ECANCON: ENHANCED CAN CONTROL REGISTER
MDSEL1
bit 7
MDSEL1:MDSEL0: Mode Select bits
00 = Legacy mode (Mode 0, default)
01 = Enhanced Legacy mode (Mode 1)
10 = Enhanced FIFO mode (Mode 2)
11 = Reserved
FIFOWM: FIFO High Water Mark bit
1 = Will cause FIFO interrupt when one receive buffer remains
0 = Will cause FIFO interrupt when four receive buffers remain
EWIN4:EWIN0: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into access bank addresses 0F60-0F6Dh.
Exact group of registers to map is determined by binary value of these bits.
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
00000 = Acceptance Filters 0, 1, 2 and BRGCON3, 2
00001 = Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010 = Acceptance Filter Masks, Error and Interrupt Control
00011 = Transmit Buffer 0
00100 = Transmit Buffer 1
00101 = Transmit Buffer 2
00110 = Acceptance Filters 6, 7, 8
00111 = Acceptance Filters 9, 10, 11
01000 = Acceptance Filters 12, 13, 14
01001 = Acceptance Filters 15
01010-01111 = Reserved
10000 = Receive Buffer 0
10001 = Receive Buffer 1
10010 = TX/RX Buffer 0
10011 = TX/RX Buffer 1
10100 = TX/RX Buffer 2
10101 = TX/RX Buffer 3
10110 = TX/RX Buffer 4
10111 = TX/RX Buffer 5
11000-11111 = Reserved
Legend:
R = Readable bit
- n = Value at POR
Note 1: These bits can only be changed in Configuration mode. See Register 19-2 to
R/W-0
2: A new mode takes into effect only after Configuration mode is exited.
3: This bit is used in Mode 2 only.
4: FIFO length of 4 or less will cause this bit to be set.
(1, 2)
change to Configuration mode.
MDSEL0
R/W-0
PIC18F6585/8585/6680/8680
(1, 2)
W = Writable bit
‘1’ = Bit is set
FIFOWM
R/W-0
(3)
EWIN4
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EWIN3
R/W-0
(4)
EWIN2
R/W-0
x = Bit is unknown
EWIN1
R/W-0
DS30491C-page 283
EWIN0
R/W-0
bit 0