S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 99

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
SCLK
10.4.6
CS#
IO0
IO1
SCLK
CS#
IO0
IO1
6
7
7
0
4 cycles
Data N
4
5
Quad I/O Read (QIOR EBh or 4QIOR ECh)
1
6
The instruction
 EBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad
Output Read command but allows input of the address bits four bits per serial SCK clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FL128S
and S25FL256S devices. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the
Quad capability of S25FL128S and S25FL256S devices.
The maximum operating clock frequency for Quad I/O Read is 104 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before
data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal
circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3
are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK and the latency code table (refer to
on page
command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC)
table. The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). However, both
latency code tables use the same latency values for the Quad I/O Read command.
Following the latency period, the memory contents at the address given, is shifted out four bits at a time
through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
2
3
2
5
Instruction
0
1
8 cycles
3
4
61). There are different ordering part numbers that select the latency code table used for this
4
3
(4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
5
2
Figure 10.35 Dual I/O Read Command Sequence
30
31
6
1
0
Figure 10.36 Continuous Dual I/O Read Command Sequence
32 Bit Address
D a t a
16 cycles
7
0
(4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
31
30
8
14
2
3
32 Bit Address
S25FL128S and S25FL256S
16 cycles
S h e e t
15
0
1
22
2
3
16
Table 8.12, Latency Codes for SDR Enhanced High Performance
6
7
23
0
1
17
4 cycles
4
5
Mode
24
6
7
18
2
3
25
4 cycles
4
5
Mode
19
0
1
26
2
3
20
2 cycles
Dummy
27
0
1
21
2 cycles
28
Dummy
22
29
6
7
23
30
4 cycles
6
7
4
5
Data 1
4 cycles
31
24
Data 1
4
5
2
3
32
2
3
25
0
1
33
0
1
26
6
7
34
6
7
27
4 cycles
4
5
Data 2
35
Data 2
4
5
28
2
3
36
2
3
0
1
99