S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 58

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

8.5
58
8.5.1
Registers
Status Register 1 (SR1)
Registers are small groups of memory cells used to configure how the S25FL-S memory device operates or
to report the status of device operations. The registers are accessed by specific commands. The commands
(and hexadecimal instruction codes) used for each register are noted in each register description. The
individual register bits may be volatile, non-volatile, or One Time Programmable (OTP). The type for each bit
is noted in each register description. The default state shown for each bit refers to the state after power-on
reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is
the value of the bit when the device is shipped from Spansion. Non-volatile bits have the same cycling (erase
and program) endurance as the main flash array.
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN
06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h).
The Status Register contains both status and control bits:
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when
this bit is set to 1 and the WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the
Status Register become read-only bits and the Write Registers (WRR) command is no longer accepted for
execution. If WP# is high the SRWD bit and BP bits may be changed by the WRR command. If SRWD is 0,
WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The SRWD bit
has the same non-volatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure
indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program
operation. This bit will also be set when the user attempts to program within a protected main memory sector
or locked OTP region. When the Program Error bit is set to a 1 this bit can be reset to 0 with the Clear Status
Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure
indication. When the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation.
This bit will also be set when the user attempts to erase an individual protected main memory sector. The
Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When
the Erase Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register (CLSR) command. This
is a read-only bit and is not affected by the WRR command.
Bits
7
6
5
4
3
2
1
0
P_ERR
E_ERR
SRWD
Name
Field
WEL
BP2
BP1
BP0
WIP
Status Register
Error Occurred
Programming
Write Disable
Write Enable
Erase Error
Protection
Function
Occurred
Progress
Write in
Block
Latch
S25FL128S and S25FL256S
Volatile if CR1[3]=1,
Volatile, Read only
Volatile, Read only
Volatile, Read only
Non-Volatile if
Non-Volatile
Table 8.8 Status Register-1 (SR1)
CR1[3]=0
Volatile
Type
D a t a
Default State
1 if CR1[3]=1,
shipped from
Spansion
0 when
S h e e t
0
0
0
0
0
1 = Locks state of SRWD, BP, and configuration register
bits when WP# is low by ignoring WRR command
0 = No protection, even when WP# is low
1 = Error occurred.
0 = No Error
1 = Error occurred
0 = No Error
Protects selected range of sectors (Block) from Program
or Erase
1 = Device accepts Write Registers (WRR), program or
erase commands
0 = Device ignores Write Registers (WRR), program or
erase commands
This bit is not affected by WRR, only WREN and WRDI
commands affect this bit
1 = Device Busy, a Write Registers (WRR), program,
erase or other operation is in progress
0 = Ready Device is in standby mode and can accept
commands
S25FL128S_256S_00_05 July 12, 2012
Description