S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 122

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

122
10.8.2
CS#
SCK
CS#
SCK
SO
SO
SI
SI
ASP Program (ASPP 2Fh)
Before the ASP Program (ASPP) command can be accepted by the device, a Write Enable (WREN)
command must be issued. After the Write Enable (WREN) command has been decoded, the device will set
the Write Enable Latch (WEL) in the Status Register to enable any write operations.
The ASPP command is entered by driving CS# to the logic low state, followed by the instruction and two data
bytes on SI, least significant byte first. The ASP Register is two data bytes in length.
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the
ASPP command is not executed. As soon as CS# is driven to the logic high state, the self-timed ASPP
operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP
operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable Latch
(WEL) is set to a 0.
MSB
MSB
7
7
0
0
6
6
1
1
5
5
2
High Impedance
2
High Impedance
Instruction
4
Instruction
4
3
3
3
3
4
4
2
5
2
5
1
Figure 10.70 ASPRD Command
1
6
Figure 10.71 ASPP Command
6
0
S25FL128S and S25FL256S
7
0
7
MSB
7
MSB
8
7
8
6
9
6
9
5
10
5
Register Out
10
D a t a
4
11
4
11
3
12
3
12
2
13
S h e e t
2
13
1
14
1
14
Register In
0
15
0
15
15
MSB
16
15
16
14
17
14
17
S25FL128S_256S_00_05 July 12, 2012
13
18
Register Out
13
18
12
19
12
19
11
20
11
20
10
21
10
21
9
22
9
22
8
23
8
23
MSB
7