S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 108

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

108
SCLK
SCLK
CS#
CS#
IO0
IO1
IO2
IO3
IO0
IO1
IO2
IO3
7
0
Figure 10.50 Continuous DDR Quad I/O Read Subsequent Access (3-byte Address,HPLC=11b)
Figure 10.49 DDR Quad I/O Read Initial Access (3-byte Address, EDh [ExtAdd=0], HPLC=11b)
20
21
22
23
The preamble is intended to give the host controller an indication about the round trip time from when the host
drives a clock edge to when the corresponding data value returns from the memory device. The host
controller will skew the data capture point during the preamble period to optimize timing margins and then use
the same skew time to capture the data during the rest of the read operation. The optimized capture point will
be determined during the preamble period of every read operation. This optimization strategy is intended to
compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP
of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4
device, both SIOs on a x2 device and the single SO output on a x1 device). This pattern was chosen to cover
both DC and AC data transition scenarios. The two DC transition scenarios include data low for a long period
of time (two half clocks) followed by a high going transition (001) and the complementary low going transition
(110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by
a high going transition (101) and the complementary low going transition (010). The DC transitions will
typically occur with a starting point closer to the supply rail than the AC transitions that may not have fully
settled to their steady state (DC) levels. In many cases the DC transitions will bound the beginning of the data
valid period and the AC transitions will bound the ending of the data valid period. These transitions will allow
the host controller to identify the beginning and ending of the valid data eye. Once the data eye has been
characterized the optimal data capture point can be chosen. See
on page 65
1
6
0
16
17
18
19
2
5
12
13
14
15
Address
for more details.
3 cycle
1
3
4
Instruction
8 cycles
10
11
8
9
4
3
4
5
6
7
2
5
2
0
1
2
3
S25FL128S and S25FL256S
6
1
4
5
6
7
1 cycle
Mode
3
0
1
2
3
7
0
D a t a
21
22
23
20
8
16
17
18
19
4
Address
3 cycles
12
13
14
15
High-Z Bus Turn-around
S h e e t
9
10
11
8
9
3 cycle Dummy
4
5
6
7
10
5
0
1
2
3
SPI DDR Data Learning Registers
4
5
6
7
1 cycle
Mode
11
0
1
2
3
S25FL128S_256S_00_05 July 12, 2012
6
12
High-Z Bus Turn-around
3 cycle Dummy
13
4
5
6
7
Data 0
7
1 cycle per data
14
0
1
2
3
4
5
6
7
Data 0
1 cycle per data
15
4
5
6
7
0
1
2
3
Data 1
8
4
5
6
7
Data 1
16
0
1
2
3
0
1
2
3