S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 77

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
10.1.4
10.1.5
10.1.6
10.1.7
10.1.3.2
Read Flash Array
Program Flash Array
Erase Flash Array
OTP, Block Protection, and Advanced Sector Protection
Register-1 command provides the state of the WIP bit. The program error (P_ERR) and erase error (E_ERR)
bits in the status register indicate whether the most recent program or erase command has not completed
successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the
device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET
commands are valid commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI)
command must be sent to return the device to standby state. CLSR clears the WIP, P_ERR, and E_ERR bits.
WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software Reset (RESET) may be used to return
the device to standby state.
Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing,
interface address length, and some aspects of data protection.
Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from
incrementally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte
address reaches the maximum address of the memory array, the read will continue at address zero of the
array.
There are several different read commands to specify different access latency and data path widths. Double
Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:
 The Read command provides a single address bit per SCK rising edge on the SI signal with read data
 Other read commands have a latency period between the address and returning data but can operate at
 The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data
 Dual or Quad Output read commands provide address a single bit per SCK rising edge on the SI / IO0
 Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data
 Fast (Single), Dual, or Quad Double Data Rate read commands provide address one bit, two bits or four
Programming data requires two commands: Write Enable (WREN), and Page Program (PP or QPP). The
Page Program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be
programmed in one operation. Programming means that bits can either be left at 1, or programmed from 1 to
0. Changing bits from 0 to 1 requires an erase operation.
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can be individually
programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide (SE) or array-wide (BE)
level.
There are commands to read and program a separate One TIme Programmable (OTP) array for permanent
data such as a serial number. There are commands to control a contiguous group (block) of flash memory
returning a single bit per SCK falling edge on the SO signal. This command has zero latency between the
address and the returning data but is limited to a maximum SCK rate of 50 MHz.
higher SCK frequencies. The latency depends on the configuration register latency code.
returning a single bit per SCK falling edge on the SO signal and may operate up to 133 MHz.
signal with read data returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.
bits per every SCK edge with read data returning one bit, two bits, or four bits of data per every SCK edge
on the IO0-IO3 signals. Double Data Rate (DDR) operation is only supported for core and I/O voltages of
3 to 3.6V.
D a t a
S25FL128S and S25FL256S
S h e e t
77