S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 88

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

88
 As part of the power up reset, hardware reset, or command reset process the AutoBoot feature
 The starting address of the boot code is selected by the value programmed into the AutoBoot Start
 At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to
 An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
 The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the
 The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.
 The AutoBoot Enable.
If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the
same manner as a Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same
manner as a Read command.
automatically starts a read access from a pre-specified address. At the time the reset process is
completed, the device is ready to deliver code from the starting address. The host memory controller only
needs to drive CS# signal from high to low and begin toggling the SCK signal. The S25FL128S and
S25FL256S device will delay code output for a pre-specified number of clock cycles before code streams
out.
Address (ABSA) field of the AutoBoot Register which specifies a 512-byte boundary aligned location; the
default address is 00000000h.
standard SPI mode; able to accept normal command operations.
ABSA field is 23 bits for devices up to 32-Gbit.
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is
– The host cannot send commands during this time.
– If ABSD = 0, the maximum SCK frequency is 50 MHz.
– If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the
– Data will continuously shift out until CS# returns high.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
needed by the host.
QUAD bit is set to 1.
SCK
CS#
SO
SI
Don’t care or High Impedance
0
Figure 10.15 AutoBoot Sequence (CR1[1]=0)
-
S25FL128S and S25FL256S
-
High Impedance
Wait State
-
tWS
-
D a t a
-
-
n
S h e e t
MSB
n+1
7
n+2
6
n+3
5
DATA OUT 1
n+4
4
S25FL128S_256S_00_05 July 12, 2012
n+5
3
n+6
2
n+7
1
n+8
0
MSB
DATA OUT 2
n+9
7