S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 85

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1,
and BP0) bits to define the size of the area that is to be treated as read-only. The Write Registers (WRR)
command also allows the user to set the Status Register Write Disable (SRWD) bit to a 1 or a 0. The Status
Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow the BP bits to be hardware
protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is
possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been
set by a Write Enable (WREN) command, regardless of the whether Write Protect (WP#) signal is driven to
the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be
considered, depending on the state of Write Protect (WP#):
 If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and
 If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and
The WP# hardware protection can be provided:
 by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic
 or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high
state. If WP# is permanently tied high, hardware protection of the BP bits can never be activated.
CS S #
SCK
SO
SI
Configuration Registers provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by
initiating a Write Enable (WREN) command.
Configuration Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write
Enable (WREN) command. Attempts to write to the Status and Configuration Registers are rejected, and
are not accepted for execution. As a consequence, all the data bytes in the memory area that are protected
by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected by WP#.
low state;
(SRWD) bit to a 1.
0
Figure 10.11 Write Registers (WRR) Command Sequence – 16 data bits
1
2
High Impedance
D a t a
I I nstruction
3
4
S25FL128S and S25FL256S
5
S h e e t
6
7
MSB
7
8
6
9
5
Status Register In
10
4
11
3
12
2
13
1
14
0
15
MSB
7
16
6
17
Configuration Register In
5
18
4
19
3
20
2
21
1
22
0
23
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