S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 60

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

60
(MHz)
Freq.
≤104
≤133
≤ 50
≤ 80
≤ 90
LC
11
00
01
10
10
Mode
0
-
-
-
-
(03h, 13h)
Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between
the end of address and the start of read data output for all read commands.
Some read commands send mode bits following the address to indicate that the next command will be of the
same type with an implied, rather than an explicit, instruction. The next command thus does not provide an
instruction byte, only a new address and mode bits. This reduces the time needed to send each command
when the same command type is repeated in a sequence of commands.
Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array
before data can be returned to the host system. Some read commands require additional latency cycles as
the SCK frequency is increased.
The following latency code tables provide different latency settings that are configured by Spansion. The High
Performance versus the Enhanced High Performance settings are selected by the ordering part number.
Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not
supported at the frequency shown. Read is supported only up to 50 MHz but the same latency value is
assigned in each latency code and the command may be used when the device is operated at  50 MHz with
any latency code setting. Similarly, only the Fast Read command is supported up to 133 MHz but the same
10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands up to
104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at
lower frequencies where a particular command is supported. The latency code values for a higher frequency
can be used for accesses at lower frequencies.
The High Performance settings provide latency options that are the same or faster than alternate source SPI
memories. These settings provide mode bits only for the Quad I/O Read command.
The Enhanced High Performance settings similarly provide latency options the same or faster than additional
alternate source SPI memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR
Dual I/O Read commands.
Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the
start of read data, if there are 5 or more dummy cycles. See
more information on the DLP.
Read
(MHz)
Freq.
≤ 50
≤ 66
≤ 66
≤ 66
Dummy
0
-
-
-
-
LC
11
00
01
10
Mode
0
0
0
0
0
(0Bh, 0Ch)
Fast Read
Table 8.10 Latency Codes for SDR High Performance
Mode
Dummy
0
0
0
0
DDR Fast Read
0
8
8
8
8
Table 8.11 Latency Codes for DDR High Performance
(0Dh, 0Eh)
S25FL128S and S25FL256S
Mode
Read Dual Out
0
0
0
0
-
Dummy
(3Bh, 3Ch)
4
5
6
7
Dummy
D a t a
0
8
8
8
-
Mode
Mode
Read Quad Out
0
0
0
0
DDR Dual I/O Read
S h e e t
0
0
0
0
-
(6Bh, 6Ch)
(BDh, BEh)
Read Memory Array Commands on page 92
Dummy
0
8
8
8
-
Dummy
4
6
7
8
S25FL128S_256S_00_05 July 12, 2012
Mode
Dual I/O Read
0
0
0
0
-
(BBh, BCh)
Dummy
Mode
4
4
5
6
-
Read DDR Quad I/O
1
1
1
1
(EDh, EEh)
Mode
Quad I/O Read
2
2
2
2
-
(EBh, ECh)
Dummy
3
6
7
8
Dummy
1
4
4
5
-
for