S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 90

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

90
10.3.14
Program NVDLR (PNVDLR 43h)
is a 0. when it is completed. When the ABWR cycle is completed, the Write Enable Latch (WEL) is set to a 0.
The maximum clock frequency for the ABWR command is 133 MHz.
Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
decoded successfully, the device will set the Write Enable Latch (WEL) to enable the PNVDLR operation.
The PNVDLR command is entered by shifting the instruction and the data byte on SI.
CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the
PNVDLR command is not executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR
operation is initiated. While the PNVDLR operation is in progress, the Status Register may be read to check
the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed
PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a program error in the
P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is
set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.
SCK
CS S #
SO
SI
SCK
CS#
SO
SI
Figure 10.19 Program NVDLR (PNVDLR) Command Sequence
MSB
7
Figure 10.18 AutoBoot Register Write (ABWR) Command
0
MSB
7
6
0
1
S25FL128S and S25FL256S
6
5
1
2
High Impedance
5
2
4
High Impedance
I I nstruction
3
Instruction
4
3
3
3
4
D a t a
4
2
2
5
5
1
1
6
6
S h e e t
0
0
7
7
MSB
MSB
7
7
8
8
6
6
9
9
AutoBoot Register
5
Data Learning Pattern
10
5
10
S25FL128S_256S_00_05 July 12, 2012
4
11
27
36
3
12
26
37
2
13
25
38
1
24
14
39
0
15