S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 109

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

Note:
1. Example DLP of 34h (or 00110100).
Note:
1. Example DLP of 34h (or 00110100).
10.5
July 12, 2012 S25FL128S_256S_00_05
SCLK
SCLK
10.5.1
10.5.2
CS#
IO0
IO1
IO2
IO3
CS#
IO0
IO1
IO2
IO3
10.5.1.1
10.5.1.2
Program Flash Array Commands
7
0
28
29
30
31
Figure 10.52 Continuous DDR Quad I/O Read Subsequent Access (4-byte Address, EHPLC=01b)
0
1
6
Program Granularity
Page Program (PP 02h or 4PP 12h)
24
25
26
27
Page Programming
Page Programming is done by loading a Page Buffer with data to be programmed and issuing a programming
command to move data from the buffer to the memory array. This sets an upper limit on the amount of data
that can be programmed with a single programming command. Page Programming allows up to a page size
(either 256 or 512 bytes) to be programmed in one operation. The page size is determined by the Ordering
Part Number (OPN). The page is aligned on the page size address boundary. It is possible to program from
one bit up to a page size in each Page programming operation. It is recommended that a multiple of 16 byte
length and aligned Program Blocks be written. For the very best performance, programming should be done
in full pages of 512 bytes aligned on 512-byte boundaries with each Page being programmed only once.
Single Byte Programming
Single Byte Programming allows full backward compatibility to the standard SPI Page Programming (PP)
command by allowing a single byte to be programmed anywhere in the memory array.
The Page Program (PP) commands allows bytes to be programmed in the memory (changing bits from 1 to
0). Before the Page Program (PP) commands can be accepted by the device, a Write Enable (WREN)
command must be issued and decoded by the device. After the Write Enable (WREN) command has been
20
21
22
23
2
5
32 Bit Address
1
4 cycles
16
17
18
19
3
4
Instruction
8 cycles
12
13
14
15
2
4
3
10
11
8
9
(4-byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b)
5
2
4
5
6
7
Figure 10.51 DDR Quad I/O Read Initial Access
3
0
1
2
3
6
1
D a t a
1 cycle
4
5
6
7
Mode
4
7
0
0
1
2
3
S25FL128S and S25FL256S
29
30
31
28
8
S h e e t
24
25
26
27
High-Z Bus Turn-around
5
20
21
22
23
32 Bit Address
9
4 cycles
16
17
18
19
12
13
14
15
10
6
10
11
8
9
4
5
6
7
11
0
1
2
3
7
1 cycle
4
5
6
7
Mode
12
7 cycle Dummy
0
1
2
3
7
7
7
7
High-Z Bus Turn-around
13
8
Optional Data Learning Pattern
6
6
6
6
14
5
5
5
5
9
15
4
4
4
4
7 cycle Dummy
7
7
7
7
3
3
3
3
16
10
Optional Data Learning Pattern
6
6
6
6
2
2
2
2
5
5
5
5
17
4
4
4
4
1
1
1
1
11
3
3
3
3
18
0
0
0
0
2
2
2
2
1
1
1
1
Data 0
4
5
6
7
1 cycle per data
19
12
0
0
0
0
0
1
2
3
Data 0
4
5
6
7
1 cycle per data
20
0
1
2
3
Data 1
4
5
6
7
13
Data 1
4
5
6
7
21
0
1
2
3
0
1
2
3
109