S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 17

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

3.2
3.3
3.4
3.5
July 12, 2012 S25FL128S_256S_00_05
Address and Data Configuration
RESET#
Serial Clock (SCK)
Chip Select (CS#)
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only
on the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will
be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2,
and IO3.
Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0
and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs
on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a
command. When RESET# is driven to logic low (V
 terminates any operation in progress,
 tristates all outputs,
 resets the volatile bits in the Configuration Register,
 resets the volatile bits in the Status Registers,
 resets the Bank Address Register to zero,
 loads the Program Buffer with all ones,
 reloads all internal configuration information necessary to bring the device to standby mode,
 and resets the internal Control Unit to standby state.
RESET# causes the same initialization process as is performed when power comes up and requires t
RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a
hardware reset should be reinitiated once the device is ready to accept a command sequence.
When RESET# is first asserted Low, the device draws I
to be held at V
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.
The RESET# input is not available on all packages options. When not available the RESET# input of the
device is tied to the inactive state, inside the package.
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in
SDR commands, and after every edge in DDR commands.
The chip select signal indicates when a command for the device is in process and the other signals are
relevant for the memory device. When the CS# signal is at the logic high state, the device is not selected and
all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or
Write Registers (WRR) embedded operation is in progress, the device will be in the Standby Power mode.
Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-
up, a falling edge on CS# is required prior to the start of any command.
SS
the device draws CMOS standby current (I
D a t a
S25FL128S and S25FL256S
S h e e t
IL
) for at least a period of t
CC1
(50 MHz value) during t
SB
).
RP
, the device:
PU
. If RESET# continues
PU
time.
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