S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 125

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
10.8.7
10.8.8
PPB Erase (PPBE E4h)
PPB Lock Bit Read (PLBRD A7h)
The PPB Erase (PPBE) command sets all PPB bits to 1. Before the PPB Erase command can be accepted by
the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the
Write Enable Latch (WEL) in the Status Register to enable any write operations.
The instruction E4h is shifted into SI by the rising edges of the SCK signal.
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of
the entire PPB memory array. Without CS# being driven to the logic high state after the eighth bit of the
instruction, the PPB erase operation will not be executed.
With the internal erase cycle in progress, the user can read the value of the Write-In Progress (WIP) bit to
check if the operation has been completed. The WIP bit will indicate a 1 when the erase cycle is in progress
and a 0 when the erase cycle has been completed. Erase suspend is not allowed during PPB Erase.
The PPB Lock Bit Read (PLBRD) command allows the PPB Lock Register contents to be read out of SO. It is
possible to read the PPB lock register continuously by providing multiples of eight clock cycles. The PPB Lock
Register contents may only be read when the device is in standby state with no other operation in progress. It
is recommended to check the Write-In Progress (WIP) bit of the Status Register before issuing a new
command to the device.
SCK
CS S #
SO
SI
CS#
SCK
SO
SI
MSB
7
D a t a
0
MSB
6
7
Figure 10.76 PPB Erase Command Sequence
1
0
S25FL128S and S25FL256S
Figure 10.75 PPBP Command Sequence
5
6
1
S h e e t
2
High Impedance
5
4
I I nstruction
2
3
High Impedance
Instruction
4
3
3
4
3
4
2
5
2
5
1
1
6
6
0
0
7
7
MSB
31
8
30
9
29
10
32 bit Address
35
3
36
2
37
1
38
0
39
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