S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 87

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
10.3.10
10.3.11
Clear Status Register (CLSR 30h)
AutoBoot
CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on
SI. Without CS# being driven to the logic high state after the eighth bit of the instruction byte has been latched
in on SI, the write disable operation will not be executed.
The Clear Status Register command resets bit SR1[5] (Erase Fail Flag) and bit SR1[6] (Program Fail Flag). It
is not necessary to set the WEL bit before the Clear SR command is executed. The Clear SR command will
be accepted even when the device remains busy with WIP set to 1, as the device does remain busy when
either error bit is set. The WEL bit will be unchanged after this command is executed.
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command.
And, in order to read boot code from an SPI device, the host memory controller or processor must supply the
read command from a hardwired state machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time
to start reading boot code.
The AutoBoot feature allows the host memory controller to take boot code from an S25FL128S and
S25FL256S device immediately after the end of reset, without having to send a read command. This saves
32 or more cycles and simplifies the logic needed to initiate the reading of boot code.
CS S #
SCK
SI
CS#
SCK
SI
Figure 10.14 Clear Status Register (CLSR) Command Sequence
D a t a
Figure 10.13 Write Disable (WRDI) Command Sequence
S25FL128S and S25FL256S
S h e e t
0
0
1
1
2
2
Instruction
Instruction
3
3
4
4
5
5
6
6
7
7
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