S25FL128SAGMFI011 Spansion, S25FL128SAGMFI011 Datasheet - Page 89

• Manufacturer Part Number: S25FL128SAGMFI011
• Description: Flash 128Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL128SAGMFI011

• Rohs: yes

July 12, 2012 S25FL128S_256S_00_05
10.3.12
10.3.13
AutoBoot Register Read (ABRD 14h)
AutoBoot Register Write (ABWR 15h)
The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on
SO, least significant byte first, most significant bit of each byte first. It is possible to read the AutoBoot
Register continuously by providing multiples of 32 clock cycles. If the QUAD bit CR1[1] is cleared to 0, the
maximum operating clock frequency for ABRD command is 133 MHz. If the QUAD bit CR1[1] is set to 1, the
maximum operating clock frequency for ABRD command is 104 MHz.
Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and
decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write
operations.
The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first,
most significant bit of each byte first. The ABWR data is 32 bits in length.
The ABWR command has status reported in Status Register-1 as both an erase and a programming
operation. An E_ERR or a P_ERR may be set depending on whether the erase or programming phase of
updating the register fails.
CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR
command is not executed. As soon as CS# is driven to the logic high state, the self-timed ABWR operation is
initiated. While the ABWR operation is in progress, Status Register-1 may be read to check the value of the
Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ABWR operation, and
SCK
IO2
IO3
IO0
IO1
CS#
SCK
CS#
SO
SI
D a t a
Figure 10.17 AutoBoot Register Read (ABRD) Command
0
MSB
-
7
0
Figure 10.16 AutoBoot Sequence (CR1[1]=1)
S25FL128S and S25FL256S
-
High Impedance
6
High Impedance
High Impedance
High Impedance
1
Wait State
S h e e t
-
5
tWS
2
High Impedance
Instruction
-
4
3
3
-
4
2
-
5
n
1
6
MSB
n+1
5
7
4
6
0
7
MSB
n+2
1
3
0
2
7
8
n+3
5
4
6
7
6
9
DATA OUT 1
n+4
1
0
2
3
AutoBoot Register
5
10
n+5
4
5
6
7
4
11
n+6
1
3
0
2
n+7
26
5
7
4
6
37
n+8
25
1
3
0
2
38
24
n+9
5
7
4
6
39
MSB
7
40
89