EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 75

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EVAL-ADUC836QS

Manufacturer Part Number
EVAL-ADUC836QS
Description
MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
Manufacturer
AD [Analog Devices]
Datasheet
Parameter
SPI MASTER MODE TIMING (CPHA = 1)
*Characterized under the following conditions:
REV. 0
Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and SPI bit rate selection bits
SPR1 and SPR0 in SPICON SFR are both set to 0.
t
t
t
t
t
t
t
t
t
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
SCLOCK Low Pulsewidth*
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
MOSI
MISO
t
DOSU
t
DSU
MSB IN
Figure 75. SPI Master Mode Timing (CPHA = 1)
MSB
t
DHD
t
SH
t
DF
t
DAV
t
SL
t
DR
BITS 6–1
BITS 6–1
–75–
Min
100
100
LSB IN
t
Typ
630
630
10
10
10
10
SR
LSB
t
SF
Max
50
25
25
25
25
ADuC836
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns

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