EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 57

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

UART SERIAL INTERFACE
The serial port is full-duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can com-
mence reception of a second byte before a previously re ceived byte
has been read from the receive register. However, if the fi rst byte
still has not been read by the time reception of the second byte is
complete, the fi rst byte will be lost. The phys i cal interface to the
serial data network is via pins RxD(P3.0) and TxD(P3.1), while
the SFR interface to the UART comprises the following registers:
SCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
UART OPERATING MODES
Mode 0: 8-Bit Shift Register Mode
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or received.
Transmission is initiated by any instruction that writes to SBUF.
The data is shifted out of the RxD line. The 8 bits are transmitted
with the least signifi cant bit (LSB) fi rst, as shown in Figure 54.
Reception is initiated when the Receive Enable bit (REN) is 1 and
the Receive Interrupt bit (RI) is 0. When RI is cleared, the data
is clocked into the RxD line and the clock pulses are out put from
the TxD line.
REV. 0
Name
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Description
UART Serial Mode Select Bits.
These bits select the Serial Port operating mode as follows:
SM0
0
0
1
1
Multiprocessor Communication Enable Bit.
Enables multiprocessor com mu ni ca tion in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if
SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon
as the byte of data has been re ceived. In Modes 2 or 3, if SM2 is set, RI will not be ac ti vat ed if the re ceived ninth
data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received.
Serial Port Receive Enable Bit.
Set by user software to enable serial port reception.
Cleared by user software to dis able serial port reception.
Serial Port Transmit (Bit 9).
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
Serial Port Receiver Bit 9.
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
Serial Port Transmit Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receive Interrupt Flag.
Set by hardware at the end of the eighth bit in Mode 0, or half way through the stop bit in Modes 1, 2, and 3.
RI must be cleared by software.
UART Serial Port Con trol Registers
98H
00H
Yes
SM1
0
1
0
1
Se lect ed Op er at ing Mode
Mode 0: Shift Register, fi xed baud rate (f
Mode 1: 8-bit UART, variable baud rate
Mode 2: 9-bit UART, fi xed baud rate (f
Mode 3: 9-bit UART, variable baud rate
Table XXX. SCON SFR Bit Designations
–57–
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register, and reading SBUF accesses a physi-
cally separate receive register.
(SHIFT CLOCK)
(DATA OUT)
Figure 54. UART Serial Port Transmission, Mode 0
CORE
CLK
ALE
RxD
TxD
CORE
CORE
S1
/64) or (f
S2
MACHINE
DATA BIT 0
/12)
CYCLE 1
S3
S4
S5
CORE
S6
S1
/32)
DATA BIT 1
S2
MACHINE
CYCLE 2
S3
S4
MACHINE
CYCLE 7
DATA BIT 6
S4
S5
ADuC836
S6
S1
S2
DATA BIT 7
MACHINE
CYCLE 8
S3
S4
S5
S6