EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

ADC SFR INTERFACE
Both ADCs are controlled and confi gured via a number of SFRs that are summarized here and described in more detail in the
fol low ing sections.
ADCSTAT
ADCMODE ADC Mode Register. Controls general modes of
ADC0CON
ADC1CON
SF
ICON
ADCSTAT (ADC Status Register)
This SFR refl ects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions
such as reference detect and conversion over fl ow/underfl ow fl ags.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
REV. 0
Name
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
–––
–––
ADC Status Register. Holds general status of the
primary and auxiliary ADCs.
operation for primary and auxiliary ADCs
Primary ADC Control Register. Controls specifi c
confi guration of primary ADC.
Auxiliary ADC Control Register. Controls
specifi c confi guration of auxiliary ADC.
Sinc Filter Register. Con fi g ures the dec ima tion
factor for the Sinc
and aux il ia ry ADC update rates.
Current Source Control Register. Al lows the user
to control of the various on-chip cur rent source
options.
Description
Ready Bit for Primary ADC.
Set by hardware on completion of ADC conversion or calibration cy cle.
Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conver sion
or calibration. The primary ADC is in hib it ed from writing further results to its data or cal i bra tion registers
until the RDY0 bit is cleared.
Ready Bit for Auxiliary ADC. Same defi nition as RDY0 referred to the auxiliary ADC.
Calibration Status Bit.
Set by hardware on com ple tion of cal i bra tion.
Cleared indirectly by a write to the mode bits to start an oth er ADC con ver sion or calibration.
No Ex ter nal Reference Bit (only active if primary or auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is fl oat ing or the applied voltage is below a specifi ed threshold.
When set, con ver sion results are clamped to all ones, if using external reference.
Cleared to indicate valid V
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data reg is ters has been clamped to all
zeros or all ones. After a calibration, this bit also fl ags error con di tions that caused the calibration registers not
to be writ ten.
Cleared by a write to the mode bits to initiate a con ver sion or cal i bra tion.
Auxiliary ADC Error Bit. Same defi nition as ERR0 referred to the auxiliary ADC.
Reserved for Future Use
Reserved for Future Use
3
fi lter and thus the pri ma ry
D8H
00H
Yes
Table IV. ADCSTAT SFR Bit Designations
REF
.
–17–
ADC0M/H
ADC1L/H
OF0M/H
OF1L/H
GN0M/H
GN1L/H
Primary ADC 16-bit con ver sion result is held in
these two 8-bit registers.
Auxiliary ADC 16-bit conversion result is held in
these two 8-bit registers.
Primary ADC 16-bit Offset Calibration Coeffi cient
is held in these two 8-bit reg is ters.
Auxiliary ADC 16-bit Offset Calibration Coeffi cient
is held in these two 8-bit reg is ters.
Primary ADC 16-bit Gain Calibration Coeffi cient
is held in these two 8-bit reg is ters.
Auxiliary ADC 16-bit Gain Calibration Coeffi cient
is held in these two 8-bit registers.
ADuC836