EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 70

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

ADuC836
TIMING SPECIFICATIONS
Parameter
CLOCK INPUT (External Clock Driven XTAL1)
NOTES
1
2
3
4
5
6
AC inputs during testing are driven at DV
Logic 0, as shown in Figure 70.
For timing purposes, a port pin is no longer fl oating when a 100 mV change from load voltage occurs. A port pin begins to fl oat when a 100 mV change from the loaded
V
C
ADuC836 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
ADuC836 Machine Cycle Time is nominally defi ned as 12/Core_Clk.
OH
LOAD
t
t
t
t
t
1/t
t
t
CK
CKL
CKH
CKR
CKF
CORE
CYC
/V
CORE
OL
for Port 0, ALE,
level occurs, as shown in Figure 70.
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC836 Core Clock Frequency
ADuC836 Core Clock Period
ADuC836 Machine Cycle Time
DV
DD
– 0.5V
0.45V
outputs = 100 pF; C
DD
– 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V
1, 2, 3
0.2DV
0.2DV
TEST POINTS
LOAD
Figure 70. Timing Waveform Characteristics
DD
DD
for all other outputs = 80 pF, unless otherwise noted.
– 0.1V
+ 0.9V
t
CKH
5
(AV
all specifi cations T
6
DD
4
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
Figure 69. XTAL1 Input
–70–
Min
0.098
0.95
t
V
MIN
CKL
LOAD
to T
V
V
32.768 kHz External Crystal
LOAD
LOAD
MAX
t
, unless otherwise noted.)
– 0.1V
+ 0.1V
CKR
t
CK
Typ
30.52
6.26
6.26
9
9
0.636
7.6
REFERENCE
POINTS
TIMING
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V;
t
CKF
Max
12.58
122.45
IH
V
V
min for a Logic 1, and V
LOAD
LOAD
– 0.1V
+ 0.1V
V
LOAD
Unit
MHz
s
s
s
s
s
s
s
IL
max for a
REV. 0