EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 45

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

SPIDAT
Function
SFR Address
Power-On Default Value
Bit Addressable
Depending on the confi guration of the bits in the SPICON SFR
shown in Table XXI, the ADuC836 SPI interface will transmit
or receive data in a number of possible modes. Figure 34 shows
all possible ADuC836 SPI confi gurations and the timing re la -
tion ships and synchronization between the signals involved. Also
shown in this fi gure is the SPI Interrupt bit (ISPI) and how it is
triggered at the end of each byte-wide communication.
REV. 0
(CPHA = 0)
(CPHA = 1)
SAMPLE INPUT
SAMPLE INPUT
DATA OUTPUT
DATA OUTPUT
Figure 34. SPI Timing, All Modes
(CPOL = 1)
(CPOL = 0)
ISPI FLAG
ISPI FLAG
SCLOCK
SCLOCK
?
MSB BIT 6 BIT 5
SPI Data Register
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read
data just received by the SPI interface.
F7H
00H
No
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
–45–
SPI Interface—Master Mode
In Master mode, the SCLOCK pin is always an output and gen-
erates a burst of eight clocks whenever user code writes to the
SPIDAT Register. The SCLOCK bit rate is determined by SPR0
and SPR1 in SPICON. It should also be noted that the
is not used in Master mode. If the ADuC836 needs to assert
the
should be used.
In Master mode, a byte transmission or reception is initiated
by a write to SPIDAT. Eight clock periods are generated via
the SCLOCK pin and the SPIDAT byte being transmitted via
MOSI. With each SCLOCK period, a data bit is also sampled
via MISO. After eight clocks, the transmitted byte will have been
completely transmitted and the input byte will be waiting in the
input shift register. The ISPI fl ag will be set automatically and an
interrupt will occur if enabled. The value in the shift register will
be latched into SPIDAT.
SPI Interface—Slave Mode
In Slave mode, the SCLOCK is an input. The
be driven low externally during the byte communication. Trans-
mis sion is also initiated by a write to SPIDAT. In Slave mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will have been completely transmitted and
the input byte will be waiting in the input shift register. The ISPI
fl ag will be set automatically and an interrupt will occur if enabled.
The value in the shift register will be latched into SPIDAT only
when the transmission/reception of a byte has been completed.
The end of transmission occurs after the eighth clock has been
received, if CPHA = 1 or when
pin on an external slave device, a port digital out put pin
returns high if CPHA = 0.
ADuC836
pin must also
pin