EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 43

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once en abled,
monitors both supplies (AV
indicate when any of the supply pins drops below one of four
user-selectable voltage trip points from 2.63 V to 4.63 V. For cor-
rect operation of the Power Sup ply Mon i tor function, AV
be equal to or greater than 2.7 V. Monitor func tion is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
PSMCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
REV. 0
Name
CMPD
CMPA
PSMI
TPD1
TPD0
TPA1
TPA0
PSMEN
Description
DV
This is a read-only bit and directly refl ects the state of the DV
Read 1 indicates the DV
Read 0 indicates the DV
AV
This is a read-only bit and directly refl ects the state of the AVDD comparator.
Read 1 indicates the AV
Read 0 indicates the AV
Power Sup ply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, in di cat ing low an a log or dig i tal
sup ply. The PSMI Bit can be used to interrupt the pro ces sor. Once CMPD and/or CMPA return (and re main)
high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be
written by the user. However, if either comparator output is low, it is not pos si ble for the user to clear PSMI.
DV
These bits select the DV
TPD1
0
0
1
1
AVDD Trip Point Se lec tion Bits.
These bits select the AV
TPA1
0
0
1
1
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the Power Supply Monitor Circuit.
Cleared to 0 by the user to disable the Power Supply Monitor Circuit.
DD
DD
DD
DD
Power Supply Monitor Con trol Register
DFH
DEH
No
Com par a tor Bit.
Trip Point Se lec tion Bits.
Comparator Bit.
or DV
DD
) on the ADuC836. It will
TPD0
0
1
0
1
TPA0
0
1
0
1
Table XX. PSMCON SFR Bit Designations
DD
DD
DD
DD
DD
DD
supply is above its selected trip point.
supply is below its selected trip point.
trip point voltage as follows:
supply is above its selected trip point.
supply is below its selected trip point.
trip point voltage as follows:
Se lect ed DV
4.63
3.08
2.93
2.63
Se lect ed AV
4.63
3.08
2.93
2.63
DD
must
–43–
DD
DD
will in ter rupt the core using the PSMI bit in the PSMCON SFR.
This bit will not be cleared until the failing power supply has
returned above the trip point for at least 250 ms. This mon i tor
func tion allows the user to save working reg is ters to avoid possible
data loss due to the low supply con di tion, and also ensures that
normal code execution will not re sume until a safe sup ply level
has been well es tab lished. The supply mon i tor is also protected
against spurious glitches trig ger ing the interrupt circuit.
Trip Point (V)
Trip Point (V)
DD
com par a tor.
ADuC836