EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 53

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

TCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
*These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external
Timer/Counter 0 and 1 Data Registers
Both Timer 0 and Timer 1 consist of two 8-bit registers. These can be used as independent registers or combined to be a sin gle 16-bit
register, de pend ing on the timer mode confi guration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
REV. 0
Name
TF1
TR1
TF0
TR0
IE1*
IT1*
IE0*
IT0*
Description
Timer 1 Overfl ow Flag.
Set by hardware on a Timer/Counter 1 overfl ow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
Timer 0 Overfl ow Flag.
Set by hardware on a Timer/Counter 0 overfl ow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external in ter rupt pin INT1, depending on bit IT1 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
ac ti vat ed. If level-activated, the external requesting source rather than the on-chip hardware, controls the request fl ag.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external in ter rupt pin INT0, depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request fl ag, rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 tran si tion).
Cleared by software to specify level-sensitive detection (i.e., zero level).
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
Table XXVII. TCON SFR Bit Designations
–53–
and
ADuC836
interrupt pins.