EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 35

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

Note that Figure 22 represents a transfer function in 0-to-V
only. In 0-to-V
would be similar, but the upper por tion of the transfer function
would follow the “ideal” line right to the end, showing no signs of
endpoint linearity errors.
The endpoint nonlinearities conceptually illustrated in Figure 22
get worse as a function of output loading. Most of the ADuC836
data sheet specifi cations assume a 10 k re sis tive load to ground
at the DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 22 become larger. With larger current demands, this
can signifi cantly limit output volt age swing. Figures 23 and 24
illustrate this behavior. It should be noted that the upper trace in
each of these fi g ures is valid only for an output range selection of
0-to-AV
side voltage drops as long as the reference voltage remains below
the upper trace in the cor re spond ing fi gure. For example, if AV
= 3 V and V
loads less than 5 mA. But somewhere around 7 mA, the upper curve
in Figure 24 drops below 2.5 V (V
higher cur rents, the output will not be capable of reaching V
REV. 0
V
V
DD
DD
–100mV
–50mV
100mV
50mV
Figure 23. Source and Sink Current Capability
with V
0mV
V
DD
Figure 22. Endpoint Nonlinearities Due to
Am pli fi er Saturation
DD
4
5
3
2
1
0
. In 0-to-V
0
REF
000H
REF
REF
= 2.5 V, the high side voltage will not be affected by
= AV
mode (with V
REF
DD
SOURCE/SINK CURRENT – mA
= 5 V
mode, DAC loading will not cause high
5
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
REF
REF
< V
), indicating that at these
DD
), the lower nonlinearity
10
DD
15
FFFH
mode
REF
DD
.
–35–
For larger loads, the current drive capability may not be suffi cient
To increase the source and sink current ca pa bil i ty of the DAC, an
external buffer should be added, as shown in Figure 25.
The DAC output buffer also features a high impedance disable func-
tion. In the chip’s default power-on state, the DAC is disabled and
its output is in a high impedance state (or “three-state”) where
they remain inactive until enabled in soft ware.
This means that if a zero output is desired during power-up or
power-down transient conditions, a pull-down resistor must be
added to each DAC output. Assuming this resistor is in place, the
DAC output will remain at ground potential when ev er the DAC
is disabled.
Figure 24. Source and Sink Current Capability with
V
REF
4
3
1
0
0
= V
Figure 25. Buffering the DAC Output
ADuC836
DD
DAC LOADED WITH 0FFFH
DAC LOADED WITH 0000H
= 3 V
SOURCE/SINK CURRENT – mA
12
5
10
ADuC836
15