SI270X-A-EVB Silicon Laboratories Inc, SI270X-A-EVB Datasheet
SI270X-A-EVB
Specifications of SI270X-A-EVB
Related parts for SI270X-A-EVB
SI270X-A-EVB Summary of contents
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... The digital input amplifier features delta-sigma PWM and innovative EMI mitigation technology for producing high-quality audio while effectively managing PWM switching noise for enhanced EMI compliance and AM/FM radio co-existence, while also being GSM/iPhone friendly. Functional Block Diagram Si270x Digital Class-D Amplifier VDD 2.7 – 3.6 V LDO Supply ...
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Si2704/05/06/07-A10 2 Rev. 0.6 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si2704/05/06/07-A10 8.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Power Output Supply Voltage Main Supply Voltage Interface (I/O) Supply Voltage Load Impedance Ambient Temperature Junction Temperature Case Delta from Junction 3 Delta from Junction to Ambient Notes: 1. All ...
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Si2704/05/06/07-A10 Table 3. DC Characteristics—Supplies and Interfaces (V = 2 1. Parameter Symbol Start Up Time T ONSB T ON_SLP T ON_PD Active Mode Quiescent I PQ Supply Current ...
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Table 4. DC Characteristics—Class D Amplifier (V = 2 1. Parameter Output Voltage Offset Total Drain-Source On-State Resistance (Total Bridge)* *Note: Excludes package bond wire resistance. Table 5. AC ...
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Si2704/05/06/07-A10 Table 5. AC Characteristics—Class D Amplifier (Continued 2 1. Power Supply Rejection Ratio Crosstalk 4 Efficiency Output Pulse Repetition Frequency Notes: 1. Measured at filter output. ...
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Figure 1. Digital Audio Timing Parameters Table 8. 2-Wire Control Interface Characteristics (V = 1. –20 to +85 °C, unless otherwise noted Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input ...
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Si2704/05/06/07-A10 Table 9. 2-Wire Control Interface Address Selection CLKO Startup Voltage (Pin Table 10. Reset Timing Characteristics (V = 1. -20 to +85 °C, unless otherwise noted Parameter CLKO Setup Time to RST↑ ...
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SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 3. 2-Wire Control Interface Read and Write Timing Parameters SCLK SDIO A6-A0, 0 (Write) START ADDRESS + R/W SDIO A6-A0, 1 (Read) START ADDRESS ...
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Si2704/05/06/07-A10 Table 11. Reference Clock and Crystal Characteristics (V = 2 1. Parameter Reference Clock, Pin XTLI 1 Supported Frequencies Frequency Tolerance 2 Jitter Tolerance High Level Input Voltage ...
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Typical Application Schematic VDD 2 0.1 uF VIO 1. XTLI X1 22 XTLO 20 RSTB 24 DFS 1 DCLK 2 DIN 4 SCLK 5 SDIO 6 CLKO SLEEP/MFP3 ...
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... Digital Audio Amplifier OUTPR OUTNR 2-Wire OUTSEL AUXOL MFP AUXOR VDD/VIO VPP XTLI XTLO OUTPL CLKO DI2 OUTNL Si270x Digital Audio 2 Amplifier I S DIN OUTPR OUTNR 2-Wire AUXOL AUXOR MFP Rev. 0.6 4.0–6.6 V Supply LF RF HPDET 4.0–6.6 V Supply Filter LF ...
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... R Tweeter R OUTSEL HPDET AUXOL Headphone AUXOR External Subwoofer AUXOL XTLI Si270x XTLO 1 Digital Audio 2 Amplifier CLKO XTLI Si270x 1 Digital Audio 2 Amplifier XTLI Si270x 1 Digital Audio 2 Amplifier XTLI Si270x 1 Digital Audio 2 Amplifier Rev. 0.6 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 15 ...
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... V power supplies. It can also drive 8 Ω bridge-tied speakers per channel with 88% efficiency. The power stage feedback systems improve power supply rejection and harmonic distortion performance. The Si270x connects up to three synchronous I configured as input or output. The I using an asynchronous sample rate converter (ASRC) and a digital crossbar mixer linearly combines any of the six ...
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... PWM Processing The Si270x is designed to operate using a bridge-tied-load (BTL) output configuration where both sides of the speaker are actively driven by the amplifier. 4.1.1. PWM Switching Rate Control The output PWM switching frequency can be programmed via 2-wire control to be half rate (480 kHz) or full rate (960 kHz) ...
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Si2704/05/06/07-A10 Figure 11. PWM CM Spectrum for Integer Mode PWM Figure 12. PWM CM Spectrum for Fractional Mode PWM 4.1.2.3. Spectral Spreading Spread mode PWM can be used to spread PWM common mode switching energy resulting in a peak energy ...
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... Interfaces,” on page 6 for additional information on startup times and power consumption. Figure 14 illustrates the device state diagram highlighting the key operating modes and the allowed transitions. For more information concerning operating modes and their programming requirements, refer to “AN469: Si270x Programming Guide”. ...
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Si2704/05/06/07-A10 POWER_DOWN Sleep Mode 4.2.2. Standby Mode Standby Mode is a reduced power state where the register states are preserved and the 2-Wire interface is fully operational, allowing for new parameters and configuration settings to be programmed even though the ...
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... Hi-Z state. These pins can be used for example to control multiplexer switches in the application via the 2-Wire bus. MFP pin function is established using the MFP_PIN_CFG command. Refer to the “AN469: Si270x Programming Guide” for more information on the options and settings requested for operation of the multi function pins. ...
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... To drive an external stereo analog amplifier (e.g., for headphones) the PWM DAC can be configured to output the main stereo channel. In this case, OUTSEL is driven low to GND. To avoid unwanted audible pop noises on the output, the Si270x implements circuitry to minimize the output transients that occur while charging and discharging the PWM DAC ac coupling capacitor (see C10 and C11 in the typical application schematic on page 13) ...
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... XTLI. A wide range of input clock frequencies are supported in this mode ranging from 2.048 to 49 MHz. Refer to Table 11 on page the “AN469: Si270x Programming Guide” for more information on the complete range of frequencies and settings required for operation on this mode. ...
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... LSB of each word before the next DFS transition and MSB of the next word. In this event, for power 2 saving slave mode DCLK sent to the Si270x can be programmed to remain low until the next DFS transition appears. The device supports both rising edge and falling edge DCLK. The number of audio bits in each audio sample defaults to 24 bits and can be configured to 16, 20 bits ...
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INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS I2S 0x00 1 DCLK DIN n n-1 MSB INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS Left-Justified 0x03 DOUT n n-1 n-2 MSB Figure 18. Left-Justified Digital Audio ...
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... To make all downstream audio processing independent of the input I sample rate converter (ASRC) normalizes the input rate to 48 kHz. Refer to the “AN469: Si270x Programming Guide” for more information on the complete range of programming parameters and settings requested for operation of the digital audio processing features. ...
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... SET_EQ_BIQUAD_FILTER_COEFF. 4.6.2. Tone Control The Si270x implements tone control in the form of two second order shelving filters for bass and treble. Each filter has programmable cut-off frequency and boost/cut gain. Cut-off frequency can be adjusted from kHz by setting properties BASS_CORNER_FREQ (for bass) and TREBLE_CORNER_FREQ (for treble). Gain can be adjusted from – ...
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Si2704/05/06/07-A10 4.6.3. De-Emphasis (Si2706/07 only) The Si2706/07 features a de-emphasis filtering option in order to be able to process recorded audio that for noise reasons has been subject to 50/15 µs pre-emphasis. The 50/15 µs filter implemented has corner frequencies ...
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... DRC_LOOKAHEAD_TIME allows setting the look ahead time that permits the DRC circuit to adjust the compression to sudden level changes thus preventing the clipping of the fast changing signal. Refer to “AN503: Si270x Class-D Amplifier—Dynamic Range Compressor Use” for additional information. Si2704/05/06/07-A10 Rev. 0.6 ...
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... Each channel has a separate dc notch filter. 4.6.9. Tone and Alert Generation The Si270x includes two independent tone generators with programmable frequencies and on/off times. The output of both tone generators is fed to a mixer which combines the tones with the I amplitudes can be adjusted by programming the mixer coefficients using the SET_AUDIO_INPUT_MIXER command ...
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... The CLKO pin serves as a configuration boot-strap to select one of two unique addresses to which the Si270x responds. During reset, if CLKO is pulled low using a 2.2 k resistor connected to ground, then the 7 bit device address is 1001010 (0x94). If CLKO is left floating k internal pull-up within the Si270x causes the 2-Wire to select a device address of 0011011 (0x36). ...
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... Si2704/05/06/07-A10 5. Commands and Properties Table 16 and Table 17 are the summary of commands and properties for the Si270x Class D Audio Amplifier device. Table 16. Class D Audio Amplifier Command Summary Number Name 0x01 POWER_UP 0x10 FUNC_INFO 0x12 SET_PROPERTY 0x13 GET_PROPERTY 0x14 MFP_PIN_CFG 0x15 SET_AUDIO_INPUT_MIXER 0x16 ...
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Table 17. Class D Audio Amplifier Property Summary (Continued) Category Number Biquad 0x1901 CROSSOVER_FREQ Filter 0x2103 BASS_BOOST_CUT 0x2104 BASS_CORNER_FREQ 0x2105 TREBLE_BOOST_CUT 0x2106 TREBLE_CORNER_FREQ Volume 0x2201 VOLUME_MUTE 0x2202 VOLUME_MASTER 0x2203 VOLUME_BALANCE 0x2204 VOLUME_AUX_CHANNEL 0x2205 VOLUME_RAMP DRC 0x2301 DRC_CONFIG 0x2302 DRC_THRESHOLD 0x2303 ...
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Si2704/05/06/07-A10 6. Pin Descriptions 6.1. 24-Pin QFN Package Pin Number Name GND PAD GND 1 DCLK 2 DIN 3 VIO 4 SCLK 5 SDIO 6 CLKO 7 MFP3 8 AUXOL 9 AUXOR 10 MFP1 11 OUTSEL/MFP2 12 VPPR 13 OUTPR ...
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Package Pin Number Name 1, 10, 11, 12, 13, NC 14, 15, 16, 23, 24, 25, 36, 37, 38, 39, 45, 46, 47 DFS 3 DCLK 4 DIN 5 VIO 6, 20, 28, 33, 43 ...
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Si2704/05/06/07-A10 Table 19. Pin Descriptions (Continued) Pin Number Name 29 OUTNR 30 GNDR 31 GNDL 32 OUTNL 34 OUTPL 35 VPPL 40 RST 41 XTLO 42 XTLI 44 VDD 36 Function Right channel power stage “N” output. Right channel power ...
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Ordering Guide Part Number* Si2704-A10-GM 2.0 EMI Mitigating Class D Power Amplifier Si2704-A10-GQ 2.0 EMI Mitigating Class D Power Amplifier Si2705-A10-GM 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio Si2705-A10-GQ 2.1 EMI Mitigating ...
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Si2704/05/06/07-A10 8. Package Outline 8.1. 24-Pin QFN Package Figure 27 illustrates the package details for 24-pin QFN package option for the Si2704/05/06/07. Table 20 lists the values for the dimensions shown in the illustration. Table 20. 24-Pin QFN Package ...
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Package Figure 28 illustrates the package details for 48-pin eTQFP package option for the Si2704/05/06/07. Table 21 lists the values for the dimensions shown in the illustration. Si2704/05/06/07-A10 Figure 28. 48-Pin eTQFP Rev. 0.6 39 ...
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Si2704/05/06/07-A10 Table 21. 48-Pin eTQFP Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC D1 7.00 BSC D2 3.71 3.81 e 0.50 BSC Notes: 1. All ...
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Package Markings (Top Marks) 9.1. Si2707 Top Mark (QFN) 9.2. Top Mark Explanation Mark Method YAG Laser Line 1 Marking Part Number Firmware Revision Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 ...
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Si2704/05/06/07-A10 9.3. Si2707 Top Mark (eTQFP) 9.4. Top Mark Explanation Mark Method YAG Laser Line 1 Marking Part Number Firmware Revision Line 2 Marking Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified) ...
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... AN469: 270x Programming Guide AN470: 270x Layout Guidelines AN502: Si270x Class-D Amplifier—Analog Source Setup AN503: Si270x Class-D Amplifier—Dynamic Range Compressor Use AN504: Si270x Class-D Amplifier—Dynamic Bass Configuration AN505: Si270x Class-D Amplifier—Measuring Output Power ...
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Si2704/05/06/07-A10 OCUMENT HANGE IST Revision 0.4 to Revision 0.5 Updated Table 3 on page 6. Updated Table 4 on page 7. Updated Table 5 on page 7. Updated Table 6 on page 8. ...
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N : OTES Si2704/05/06/07-A10 Rev. 0.6 45 ...
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