EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 37

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

PWM MODES OF OPERATION
Mode 0: PWM Disabled
The PWM is disabled, allowing P1.0 and P1.1 to be used as nor mal.
Mode 1: Single Variable Resolution PWM
In Mode 1, both the pulse length and the cycle time (period) are
programmable in user code, allowing the resolution of the PWM
to be variable.
PWM1H/L sets the period of the output waveform. Reducing
PWM1H/L reduces the resolution of the PWM output but
increases the maximum output rate of the PWM (e.g., setting
PWM1H/L to 65536 gives a 16-bit PWM with a maximum
output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L
to 4096 gives a 12-bit PWM with a max i mum output rate of
3072 Hz (12.583 MHz/4096)).
PWM0H/L sets the duty cycle of the PWM output waveform, as
shown in Figure 27.
Mode 2: Twin 8-Bit PWM
In Mode 2, the duty cycle of the PWM outputs and the res o lu tion
of the PWM outputs are both programmable. The max i mum
resolution of the PWM output is eight bits.
PWM1L sets the period for both PWM outputs. Typically this will
be set to 255 (FFH) to give an 8-bit PWM, although it is possible
to reduce this as necessary. A value of 100 could be loaded here
to give a percentage PWM (i.e., the PWM is ac cu rate to 1%).
The outputs of the PWM at P1.0 and P1.1 are shown in Figure 28.
As can be seen, the output of PWM0 (P1.0) goes low when the
PWM counter equals PWM0L. The output of PWM1 (P1.1)
goes high when the PWM counter equals PWM1H and goes low
again when the PWM counter equals PWM0H. Setting PWM1H
to 0 ensures that both PWM out puts start simultaneously.
REV. 0
Figure 27. PWM in Mode 1
PWM COUNTER
PWM1H/L
PWM0H/L
P1.0
0
–37–
Mode 3: Twin 16-Bit PWM
In Mode 3, the PWM counter is fi xed to count from 0 to 65536,
giving a fi xed 16-bit PWM. Operating from the 12.58 MHz core
clock results in a PWM output rate of 192 Hz. The duty cycle of the
PWM outputs at P1.0 and P1.1 is in de pen dent ly pro gram ma ble.
As in Figure 29, while the PWM counter is less than PWM0H/L,
the output of PWM0 (P1.0) is high. Once the PWM counter
equals PWM0H/L, PWM0 (P1.0) goes low and remains low until
the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/L, the
output of PWM1 (P1.1) is high. Once the PWM counter equals
PWM1H/L, PWM1 (P1.1) goes low and remains low until the
PWM counter rolls over.
In this mode, both PWM outputs are synchronized (i.e., once the
PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1
(P1.1) will go high).
Figure 28. PWM Mode 2
Figure 29. PWM Mode 3
PWM COUNTER
PWM COUNTER
ADuC836
65536
PWM1H/L
PWM0H/L
0
P1.0
P1.1
PWM1L
PWM0H
PWM0L
PWM1H
P1.0
P1.1
0