EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 23

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION
Overview
The ADuC836 incorporates two independent - ADCs (primary
and auxiliary) with on-chip digital fi ltering intended for the mea-
surement of wide dynamic range, low fre quen cy signals such as
those in weigh-scale, strain gage, pres sure transducer, or tempera-
ture measurement applications.
Primary ADC
This ADC is intended to convert the primary sensor input. The
input is buffered and can be programmed for one of eight input
ranges from ±20 mV to ±2.56 V being driven from one of three
differential input channel options AIN1/2, AIN3/4, or AIN3/2.
The input channel is internally buffered, allowing the part to
handle signifi cant source impedances on the analog input and
REV. 0
USER TO EASILY DETECT
CURRENTS ALLOW THE
BURNED OUT OR GONE
IF A TRANSDUCER HAS
TWO 100nA BURNOUT
BURNOUT CURRENTS
OPEN-CIRCUIT.
FULLY DIFFERENTIAL PAIR OPTIONS AND
ADDITIONAL INTERNAL SHORT OPTION
(AIN2–AIN2). THE MULTIPLEXER IS
CONTROLLED VIA THE CHANNEL
A DIFFERENTIAL MULTIPLEXER
ALLOWS SELECTION OF THREE
SELECTION BITS IN ADC0CON.
ANALOG MULTIPLEXER
AIN1
AIN2
AIN3
AIN4
ANALOG INPUT CHOPPING
ALTERNATELY REVERSED
EXCELLENT ADC OFFSET
CONVERSION CYCLE.
AND OFFSET DRIFT
CHOPPING YIELDS
THE INPUTS ARE
PERFORMANCE.
MUX
THROUGH THE
AGND
AV
DD
CHOP
IMPEDANCE INPUT STAGE
FOR THE ANALOG INPUTS,
THE BUFFER AMPLIFIER
ALLOWING SIGNIFICANT
BUFFER AMPLIFIER
EXTERNAL SOURCE
GAIN AMPLIFIER ALLOWS
PRESENTS A HIGH
RANGES FROM 20mV TO
PROGRAMMABLE GAIN
2.56V (EXT V
THE PROGRAMMABLE
EIGHT UNIPOLAR AND
EIGHT BIPOLAR INPUT
IMPEDANCES.
BUFFER
AMPLIFIER
Figure 7. Primary ADC Block Diagram
REF
PGA
REFIN(–) REFIN(+)
= 2.5V).
OF WHICH IS ALSO CHOPPED)
CIRCUITRY TESTS FOR OPEN OR
THE MODULATOR PROVIDES
DATA STREAM (THE OUTPUT
REPRESENTS THE SAMPLED
THE DUTY CYCLE OF WHICH
SHORTED REFERENCE INPUTS.
SELECTED VIA THE XREF0 BIT
ANALOG INPUT VOLTAGE.
OPERATION. THE EXTERNAL
A HIGH FREQUENCY 1-BIT
THE EXTERNAL REFERENCE
TO THE DIGITAL FILTER,
FACILITATES RATIOMETRIC
INPUT TO THE ADuC836 IS
REFERENCE VOLTAGE IS
MODULATOR
REFERENCE DETECT
–23–
DIFFERENTIAL AND
- MODULATOR
DIFFERENTIAL
IN ADC0CON.
REFERENCE
-
allowing R/C fi ltering (for noise rejection or RFI reduction) to be
placed on the analog inputs if required. On-chip burnout cur rents
can also be turned on. These currents can be used to check that
a transducer on the selected channel is still op er a tion al before
attempting to take measurements.
The ADC employs a - conversion technique to realize up to
16 bits of no missing codes performance. The - modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
low-pass fi lter is then employed to decimate the modulator output
data stream to give a valid data conversion result at programmable
output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A
chopping scheme is also employed to minimize ADC offset errors.
A block diagram of the primary ADC is shown in Figure 7.
- ADC
PROGRAMMABLE
DIGITAL
FILTER
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
THE -
RATE AND BANDWIDTH OF THIS
CHOPPED TO REMOVE
FILTER ARE PROGRAMMABLE
ENSURES 24 BITS NO
MISSING CODES. THE
THE SINC 3 FILTER REMOVES
ENTIRE -
DRIFT ERROR.
PROGRAMMABLE
VIA THE SF SFR.
DIGITAL FILTER
ARCHITECTURE
- ADC
CHOP
ADC IS
AVERAGE
OUTPUT
AS PART OF THE CHOPPING
WITH ITS PREDECESSOR
IMPLEMENTATION, EACH
SUMMED AND AVERAGED
TO NULL ADC CHANNEL
DATA-WORD OUTPUT
FROM THE FILTER IS
OUTPUT AVERAGE
OFFSET ERRORS.
THE OUPUT WORD FROM THE
DIGITAL FILTER IS SCALED
THE CONVERSION RESULT.
COEFFICIENTS BEFORE
BY THE CALIBRATION
BEING PROVIDED AS
ADuC836
OUTPUT SCALING
SCALING
OUTPUT
3
programmable
RESULT WRITTEN
DIGTAL OUTPUT
TO ADC0H/M/L
SFRS