EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

MEMORY ORGANIZATION
The ADuC836 contains four different memory blocks:
(1) Flash/EE Program Memory
The ADuC836 provides 62 Kbytes of Flash/EE program mem-
o ry to run user code. The user can choose to run code from this
internal memory or run code from an external pro gram memory.
If the user applies power or resets the device while the
pulled low externally, the part will execute code from the ex ter nal
program space; otherwise, if
defaults to code execution from its internal 62 Kbytes of Flash/EE
program memory.
Unlike the ADuC816, where code execution can overfl ow from the
internal code space to external code space once the PC becomes
greater than 1FFFH, the ADuC836 does not support the rollover
from F7FFH in internal code space to F800H in external code
space. Instead, the 2048 bytes between F800H and FFFFH will
appear as NOP instructions to user code.
Permanently embedded fi rmware allows code to be serially down-
loaded to the 62 Kbytes of internal code space via the UART serial
port while the device is in-circuit. No external hardware is required.
56 Kbytes of the program memory can be reprogrammed dur ing
runtime; thus the code space can be upgraded in the fi eld using a
user defi ned protocol or it can be used as a data mem o ry. This
is discussed in more detail in the Flash/EE Memory section.
(2) Flash/EE Data Memory
4 Kbytes of Flash/EE Data Memory are available to the user and
can be accessed indirectly via a group of registers mapped into the
Special Function Register (SFR) area. Access to the Flash/EE Data
memory is discussed in detail in the Flash/EE Memory section.
(3) General-Purpose RAM
The general-purpose RAM is divided into two separate mem o ries:
the upper and lower 128 bytes of RAM. The lower 128 bytes of
RAM can be accessed through direct or indirect addressing; the
upper 128 bytes of RAM can only be accessed through indirect
addressing as it shares the same address space as the SFR space,
which can only be accessed through direct addressing.
The lower 128 bytes of internal data memory are mapped as shown
in Figure 2. The lowest 32 bytes are grouped into four banks of
eight registers addressed as R0 through R7. The next 16 bytes
(128 bits), locations 20H through 2FH above the register banks,
form a block of directly addressable bit locations at bit addresses
00H through 7FH. The stack can be located anywhere in the inter-
nal memory address space, and the stack depth can be expanded
up to 2048 bytes.
GENERAL NOTES PERTAINING TO THIS DATA SHEET
1. SET im plies a Logic 1 state and CLEARED implies a Logic 0 state, unless
2. SET and CLEARED also imply that the bit is set or automatically cleared by
3. User software should not write 1s to reserved or unimplemented bits as they
4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP
REV. 0
otherwise stated.
the ADuC836 hardware, unless otherwise stated.
may be used in future products.
package, unless otherwise stated.
62 Kbytes of On-Chip Flash/EE Program Memory
4 Kbytes of On-Chip Flash/EE Data Memory
256 bytes of General-Purpose RAM
2 Kbytes of Internal XRAM
is pulled high externally, the part
pin is
–13–
Reset initializes the stack pointer to location 07H. Any call or push
pre-increments the SP before loading the stack. Therefore, loading
the stack starts from location 08H, which is also the fi rst register
(R0) of register bank 1. Thus, if one is going to use more than one
register bank, the stack pointer should be ini tial ized to an area of
RAM not used for data stor age.
(4) Internal XRAM
The ADuC836 contains 2 Kbytes of on-chip extended data mem-
o ry. This memory, although on-chip, is accessed via the MOVX
instruction. The 2 Kbytes of internal XRAM are mapped into the
bottom 2 Kbytes of the external address space if the CFG836.0
bit is set. Otherwise, access to the external data mem o ry will occur
just like a standard 8051.
Even with the CFG836.0 bit set, access to the external XRAM
will occur once the 24-bit DPTR is greater than 0007FFH.
BITS IN PSW
Figure 2. Lower 128 Bytes of Internal Data Memory
SELECTED
BANKS
VIA
FFFFFFH
000000H
Figure 3. Internal and External XRAM
10
11
01
00
CFG836.0 = 0
EXTERNAL
ADDRESS
MEMORY
SPACE)
SPACE
(24-BIT
30H
20H
18H
10H
08H
00H
DATA
7FH
2FH
1FH
0FH
17H
07H
FFFFFFH
0007FFH
000800H
000000H
GENERAL-PURPOSE
AREA
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS
R0–R7
RESET VALUE OF
STACK POINTER
ADuC836
CFG836.0 = 1
EXTERNAL
ADDRESS
2 KBYTES
MEMORY
ON-CHIP
SPACE)
SPACE
(24-BIT
XRAM
DATA