EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

When accessing the internal XRAM, the P0 and P2 port pins, as
well as the
dard 8051 MOVX instruction. This allows the user to use these
port pins as standard I/O.
The upper 1792 bytes of the internal XRAM can be confi gured
to be used as an extended 11-bit stack pointer. By default, the
stack will operate exactly like an 8052 in that it will roll over from
FFH to 00H in the general-purpose RAM. On the ADuC836
however, it is possible (by setting CFG836.7) to enable the 11-bit
extended stack pointer. In this case, the stack will roll over from
FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is
visible in the SP and SPH SFRs. The SP SFR is located at 81H
as with a standard 8052. The SPH SFR is lo cat ed at B7H. The
3 LSBs of this SFR contain the three extra bits nec es sary to
ex tend the 8-bit stack point er into an 11-bit stack point er.
External Data Memory (External XRAM)
Just like a standard 8051 compatible core, the ADuC836 can
access external data memory using a MOVX instruction. The
MOVX instruction automatically outputs the various control
strobes required to access the data memory.
The ADuC836, however, can access up to 16 Mbytes of external
data memory. This is an enhancement of the 64 Kbytes external
data memory space available on a standard 8051 compatible core.
The external data memory is discussed in more detail in the
ADuC836 Hardware Design Considerations section.
ADuC836
Figure 4. Extended Stack Pointer Operation
CFG836.7 = 0
and
FFH
00H
ON-CHIP DATA
256 BYTES OF
(DATA +
STACK)
strobes, will not be output as per a stan-
RAM
CFG836.7 = 1
07FFH
100H
00H
(DATA + STACK
ON-CHIP XRAM
ON-CHIP XRAM
FOR EXSP = 0)
FOR EXSP = 1,
(DATA ONLY)
UPPER 1792
DATA ONLY
LOWER 256
BYTES OF
BYTES OF
–14–
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only. It
provides an interface between the CPU and all on-chip pe riph -
er als. A block diagram showing the programming model of the
ADuC836 via the SFR area is shown in Figure 5.
All registers, except the Program Counter (PC) and the four
gen er al-purpose register banks, reside in the SFR area. The SFR
registers include control, confi guration, and data registers that
provide an interface between the CPU and all on-chip pe riph er als.
Accumulator SFR (ACC)
ACC is the Accumulator Register, which is used for math
op er a tions including addition, subtraction, integer multiplication,
and division, and Boolean bit ma nip u la tions. The mnemonics for
accumulator-specifi c instructions, refer to the Accumulator as A.
B SFR (B)
The B Register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratch pad register.
Data Pointer (DPTR)
The Data Pointer is made up of three 8-bit registers, named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
used to provide memory addresses for internal and external code
access and external data access. It may be manipulated as a 16-bit
register (DPTR = DPH, DPL), although INC DPTR instructions
will automatically carry over to DPP, or as three independent 8-bit
registers (DPP, DPH, DPL).
The ADuC836 supports dual data pointers. For more information,
refer to the Dual Data Pointer section.
62 KBYTE ELECTRICALLY
NONVOLATILE FLASH/EE
REPROGRAMMABLE
PROGRAM MEMORY
256 BYTES RAM
COMPATIBLE
2K XRAM
CORE
8051
Figure 5. Programming Model
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
REPROGRAMMABLE
CURRENT SOURCES
FLASH/EE DATA
OTHER ON-CHIP
DUAL - ADCs
ELECTRICALLY
TEMP SENSOR
NONVOLATILE
PERIPHERALS
12-BIT DAC
SERIAL I/O
WDT, PSM
MEMORY
4 KBYTE
TIC, PLL
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