EVAL-ADUC836QS AD [Analog Devices], EVAL-ADUC836QS Datasheet - Page 34

• Manufacturer Part Number: EVAL-ADUC836QS
• Description: MicroConverter, Dual 16-Bit ADCs with Embedded 62 kB Flash MCU
• Manufacturer: AD [Analog Devices]

DAC
The ADuC836 incorporates a 12-bit voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of driving
10 k /100 pF. It has two selectable ranges, 0 V to V
nal band gap 2.5 V reference) and 0 V to AV
in 12-bit or 8-bit mode. The DAC has a control reg is ter, DACCON,
and two data registers, DACH/L. The DAC output can be
Bit
7
6
5
4
3
2
1
0
DACH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
Using the D/A Converter
The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifi er, the func tion al
equivalent of which is illustrated in Figure 21.
ADuC836
Figure 21. Resistor String DAC Functional Equivalent
AV
V
Name
–––
–––
–––
DACPIN
DAC8
DACRN
DACEN
REF
DD
R
R
R
R
R
Description
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
DAC Output Pin Select.
Set by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC out put to Pin 3 (P1.2/DAC/IEXC1).
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs
of the DAC, and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit.
Set by user to confi gure DAC range of 0 to AV
Cleared by user to confi gure DAC range of 0 V to 2.5 V (V
DAC Clear Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to reset DAC data registers DACL/H to zero.
DAC Enable Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to power down the DAC.
DAC Data Registers
DAC Data Registers, written by user to update the DAC output.
DACL (DAC Data Low Byte)
DACH (DAC Data High Byte)
00H
No
ADuC836
(FROM MCU)
OUTPUT
BUFFER
DISABLE
HIGH-Z
DD
Table XV. DACCON SFR Bit Designations
12
. It can operate
DAC
REF
(the inter-
FBH
FCH
Both Registers
Both Registers
–34–
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC volt age output will be updated
as soon as the DACL data SFR has been writ ten; therefore, the
DAC data registers should be up dat ed as DACH fi rst, followed
by DACL. The 12-bit DAC data should be written into DACH/L
right-jus ti fi ed such that DACL con tains the lower eight bits, and
the lower nibble of DACH con tains the upper four bits.
Features of this architecture include inherent guaranteed mono to -
nic i ty and excellent differential linearity. As illustrated in Fig ure 21,
the reference source for the DAC is user selectable in software. It
can be either AV
transfer function spans from 0 V to the voltage at the AV
In 0-to-V
0 V to the internal V
features a true rail-to-rail output stage im ple men ta tion. This means
that, un load ed, each output is capable of swinging to within less than
100 mV of both AV
ity spec i fi ca tion (when driving a 10 k resistive load to ground)
is guar an teed through the full transfer function except codes 0
to 48 in 0-to-V
V
Linearity degradation near ground and V
of the output amplifi er, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 22. The
dotted line in Figure 22 indicates the ideal transfer func tion, and
the solid line represents what the transfer func tion might look
like with endpoint nonlinearities due to saturation of the output
amplifi er.
DD
DD
.
mode.
REF
mode, the DAC out put transfer function spans from
REF
REF
DD
).
mode and 0 to 100 and 3950 to 4095 in 0-to-
or V
REF
DD
and ground. Moreover, the DAC’s linear-
REF
(2.5 V). The DAC output buffer amplifi er
. In 0-to-AV
DD
DD
mode, the DAC output
is caused by sat u ra tion
DD
pin.
REV. 0