HD6432670 Hitachi, HD6432670 Datasheet - Page 940

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Item
7.3.4 DMA Control
Registers (DMACRA and
DMACRB)
Full Address Mode
7.3.4 DMA Control
Registers (DMACRA and
DMACRB)
Full Address Mode
DMACR_0B and
DMACR_1B
7.3.5
Control Registers H and L
(DMABCRH and
DMABCRL)
Full Address Mode
7.3.5 DMA Band Control
Registers H and L
(DMABCRH and
DMABCRL)
Full Address Mode
7.3.7 DMA Terminal
Control Register
(DMATCR)
7.4.1 Activation by
Internal Interrupt Request
7.5.11 Write Data Buffer
Function
8.3.4 EXDMA Mode
Control Register (EDMDR)
9.2.6 DTC Transfer
Count Register B (CRB)
Rev. 2.0, 04/02, page 894 of 906
DMA Band
Page
266
267
271 to
273
277,
278
281
283
319
340
397
Revisions (See Manual for Details)
Description of DMACR changed.
Bits 10 to 8, 7, 4: This bit (These bits) can be read from or
written to. However, the write value should always be 0.
Desctiption of bits DTF3 to DTF0 added.
0010: Activated by
a low level in the first transfer after transfer is enabled)
Descriptions of DMABCRH changed.
Bits 13, 12, 10, 8: This bit (These bits) can be read from or
written to. However, the write value should always be 0.
Descriptions of bits 3 to 0 in DMABCRL changed.
Bit 3: (Error) If the DTIE1B bit is set to 1 when DTME1 = 0,
(Correction) If the DTME1 bit is cleared to 0 when DTIE1B =
1,
Bit 2: (Error) If the DTIE1A bit is set to 1 when DTE1 = 0,
(Correction) If the DTE1 bit is cleared to 0 when DTIE1A= 1,
Bit 1: (Error) If the DTIE0B bit is set to 1 when DTME0 = 0,
(Correction) If the DTME0 bit is cleared to 0 when DTIE0B=
1,
Bit 0: (Error) If the DTIE0A bit is set to 1 when DTE0 = 0,
(Correction) If the DTE0 bit is cleared to 0 when DTIE0A = 1,
Description on DMATCR added.
With ADI, TXI, and RXI interrupts,
When an interrupt request signal for DMAC activation is also
used for an interrupt request to the CPU or DTC activation
(DTA = 0),
DMAC internal-to-external dual address transfers and single
address transfers can be executed
transfer and internal accesses
Desription changed.
Bits 1, 0: These bits are always read as 0. The initial values
should not be modified.
Description added.
This register is not available in normal and repeat modes.
, dual address transfer external write cycles or single
pin falling edge input (detected as