HD6432670 Hitachi, HD6432670 Datasheet - Page 803

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip
2. After matching the bit rates, the chip transmits one H’00 byte to the host to indicate the end of
3. When boot mode is used, the flash memory programming control program must be prepared in
4. Before branching to the programming control program, the chip terminates transfer operations
5. In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are
Notes: 1. In boot mode, a part of the on-chip RAM area (H’FF8000 to H’FF87FF) is used by the
measures the low-level period of asynchronous SCI communication data (H’00) transmitted
continuously from the host. The chip then calculates the bit rate of transmission from the host,
and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop
bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should
be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states
before the chip is ready to measure the low-level period.
bit rate adjustment. The host should confirm that this adjustment end indication (H’00) has
been received normally, and transmit one H’55 byte to the chip. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 19.6.
the host beforehand. Prepare a programming control program in accordance with the
description in section 19.8, Flash Memory Programming/Erasing.
by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of program data or verify data with the host. The TxD pin is high. The contents of the CPU
general registers are undefined immediately after branching to the programming control
program. These registers must be initialized at the beginning of the programming control
program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
erased. Boot mode is used for the initial programming in the on-board state or for a forcible
return when a program that is to be initiated in user program mode was accidentally erased and
could not be executed in user program mode.
4.
2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after
3. Do not change the MD pin input levels in boot mode.
All interrupts are disabled during programming or erasing of the flash memory.
boot program. Addresses H’FF8800 to H’FFBFFF is the area to which the
programming control program is transferred from the host. The boot program area
cannot be used until the execution state in boot mode switches to the programming
control program.
waiting at least 20 states since driving the reset pin low. Boot mode is also cleared
when the WDT overflow reset occurs.
Rev. 2.0, 04/02, page 757 of 906