HD6432670 Hitachi, HD6432670 Datasheet - Page 351

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

7.5.8
An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As like CPU cycles, DMA cycles conform to the bus controller
settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
7.5.9
Short Address Mode: Figure 7.18 shows a transfer example in which
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
Basic Bus Cycles
DMA Bus Cycles (Dual Address Mode)
Address bus
CPU cycle
Figure 7.17 Example of DMA Transfer Bus Timing
ø
T
1
address
Source
T
2
DMAC cycle (1-word transfer)
T
1
T
Destination address
2
T
3
T
1
T
2
T
Rev. 2.0, 04/02, page 305 of 906
3
CPU cycle
output is enabled